X9271_11 INTERSIL | Alldatasheet
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FN8174.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2005, 2011. All Rights Reserved XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. X9271 Single Supply/Low Power/256-Tap/SPI Bus Single, Digitally Controlled (XDCP™) Potentiometer
FEATURES
- 256 Resistor Taps
- SPI Serial Interface for Write, Read, and Transfer Operations of Potentiometer
- Wiper Resistance, 100Ω typical @ VCC = 5V
- 16 Nonvolatile Data Registers
- Nonvolatile Storage of Multiple Wiper Positions
- Power-on Recall; Loads Saved Wiper Position on Power-up
- Standby Current < 3µA Max CC = 2.7V to 5.5V Operation
- 5 0 kΩ, 100kΩ Versions of End-to-End Resistance
- 100-yr Data Retention
- Endurance: 100,000 Data Changes per Bit per Register
- 14-Lead TSSOP
- Low-power CMOS
- Pb-free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9271 integrates a si ngle, digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented by using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to and read by the user. The contents of the WCR control the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications. including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM 50kΩ and 100kΩ RH RLRW POT VCC VSS SPI Bus Power-on Recall Wiper Counter Register (WCR) Data Registers
16 Bytes
256 Taps
Data Sheet June 23, 2011
2 FN8174.3 June 23, 2011
Ordering Information
(Notes 1, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP. RANGE (°C) PACKAGE PKG. DWG. # X9271UV14IZ (Note 2) X9271 UVZI 5 ±10% 50 -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9271UV14Z (Note 2) X9271 UVZ 5 ±10% 50 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9271TV14 (Note 4) X9271 TV 5 ±10% 100 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9271TV14IZ (Note 2) X9271 TVZI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9271TV14Z (Note 2) X9271 TVZ 5 ±10% 100 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363. 4. Not recommended for new designs. X9271
3 FN8174.3 June 23, 2011 DETAILED FUNCTIONAL DIAGRAM CIRCUIT-LEVEL APPLICATIONS
- Vary the gain of a voltage amplifier.
- Provide programmable DC reference voltages for comparators and detectors.
- Control the volume in audio circuits.
- Trim out the offset voltage error in a voltage amplifier circuit.
- Set the output voltage of a voltage regulator.
- Trim the resistance in Wheatstone bridge circuits.
- Control the gain, characteristic frequency, and Q-factor in filter circuits.
- Set the scale factor and zero point in sensor signal conditioning circuits.
- Vary the frequency and duty cycle of timer ICs.
- Vary the DC biasing of a pin diode attenuator in RF circuits.
- Provide a control variable (I, V, or R) in feedback circuits. SYSTEM-LEVEL APPLICATIONS
- Adjust the contrast in LCD displays.
- Control the power level of LED transmitters in communication systems.
- Set and regulate the DC biasing point in an RF power amplifier in wireless systems.
- Control the gain in audio and home entertainment systems.
- Provide the variable DC bias for tuners in RF wireless systems.
- Set the operating points in temperature control systems.
- Control the operating point for sensors in industrial systems.
- Trim offset and gain errors in artificial intelligence systems. R0 R1 R2 R3 Wiper Counter Register (WCR) RH RL DATA RW Interface and Control Circuitry VCC VSS Bank 0 R0 R1 R2 R3 Bank 1 R0 R1 R2 R3 Bank 2 R0 R1 R2 R3 Bank 3
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
50kΩ and 100kΩ Power-on Recall X9271
4 FN8174.3 June 23, 2011 PIN CONFIGURATION PIN ASSIGNMENTS VCC RL VSS RW SCK CS TSSOP RH X9271 NC SI HOLD WP TSSOP Symbol Function
1 SO Serial Data Output
2 A0 Device Address
3 NC No Connect
5 SCK Serial Clock
6 SI Serial Data Input
8W P Hardware Write Protect
9 A1 Device Address
10 HOLD Device Select. Pause the serial bus.
11 R W Wiper Terminal of Potentiometer
12 R H High Terminal of Potentiometer
13 R L Low Terminal of Potentiometer
14 V CC System Supply Voltage
5 FN8174.3 June 23, 2011 PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) The Serial Output (SO) is the serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by t he falling edge of the serial clock. SERIAL INPUT (SI) The Serial Input (SI) is the serial data input pin. All operational codes, byte addresses, and data to be written to the potentiometers and potentiometer registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The Serial Clock (SCK) input is used to clock data into and out of the X9271. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is under way, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. DEVICE ADDRESS (A1 - A0) The Device Address (A1 - A0) inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initia te communication with the X9271. CHIP SELECT (CS) When Chip Select (CS) is HIGH, the X9271 is deselected, the SO pin is at high impedance, and (unless an internal write cycle is under way) the device is in standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin (R W) is equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The System Supply Voltage (V CC) pin is the system supply voltage. The Supply Ground (V SS) pin is the system ground. Other Pins HARDWARE WRITE PROTECT INPUT (WP) The Hardware Write Protect Input (WP ) pin, when LOW, prevents nonvolatile writes to the data registers. NO CONNECT No Connect pins should be left floating. These pins are used for Intersil manufacturing and testing purposes. X9271
during the entire operation. The X9271 is composed of a resistor array (Figure 1). switch may be turned on at a time. specification is always in effect. FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
- It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
- It can be written indirectly by transferring the contents of
Register instruction (parallel load).
- It can be modified one step at a time by the Increment/
- It is loaded with the contents of its Data Register zero
parameters or user preference data. WIP: Write In Progress status bit; read only. TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
There are 16 registers organized into four banks. Counter Register operations. Wiper Counter Register (Tables 5 and 6). TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3) TABLE 7. INSTRUCTION BYTE FORMAT
- Set to P0 = 0 for potentiometer operations.
9 FN8174.3 June 23, 2011 DEVICE DESCRIPTION Instructions Five of the eight instructio ns are three bytes in length. These instructions are: – Read Wiper Counter Register: Read the current wiper position of the potentiometer. – Write Wiper Counter Register: Change current wiper position of the potentiometer. – Read Data Register: Read the contents of the selected Data Register. – Write Data Register: Write a new value to the selected Data Register. – Read Status: This command returns the contents of the WIP bit, which indicates if the internal write cycle is in progress. See Table 8 for details of the instruction set. The basic sequence of the 3-byte instruction is shown in Figure 2. These 3-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, wit h the static RAM controlling the wiper position. The response of the wiper to this action is delayed by t WRL. A transfer from the WCR (current wiper position) to a Data Register is a write to nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers, or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (Figure 3). Two instructions require a 2-byte sequence to complete (Figure 4). These instructions transfer data between the host and the X9271; either between the host and one of the data registers, or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register: Transfers the contents of one specified Data Regis- ter to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register: Transfers the contents of the specified Wiper Coun- ter Register to the associated Data Register. The final command is Increment/Decrement (Figures 5 and 6). It is different from the other commands, because its length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment step, thereby providing a fine-tun ing capability to the host. For each SCK clock pulse (t HIGH) while SI is HIGH, the selected wiper moves one resistor segment towards the R H terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one resistor segment towards the R L terminal. Write-in-Process (WIP) Bit The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by the Write-in-Process bit (WIP). The WIP bit is read with a Read Status command. X9271
12 FN8174.3 June 23, 2011 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Wiper Position (Sent by X9271 on SO) CS Rising Edge010100 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge01010 0 A 1 A 0 10100000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge0 1 0 100 A 1 A 0 1011 R B R A P 1 P 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 0 A 1A 0 1 1 0 0R BR AP 1 P 0 D 7D 6D 5D 4D 3D 2D 1D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 100A 1A 01110R B R A 0 0 X9271
13 FN8174.3 June 23, 2011 Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 6, 7) Increment/Decrement Wiper Counter Register (WCR) (Notes 6, 7, 8, 9, 10) Read Status Register (SR) (Note 6) NOTES: 6. “A1 ~ A0”: stands for the device addresses sent by the master. 7. WCRx refers to wiper position data in the Wiper Counter Register. 8. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high). 9. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high). 10. “X:”: Don’t Care. CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge01010 0A 1 A 01 1 0 1 R BR A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) CS Rising Edge0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge01010 0A 1A 0 010100010000000 W I P X9271
14 FN8174.3 June 23, 2011 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, any address input, http://www.intersil.com/pbfree/Pb-FreeReflow.asp COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) NOTES: 11. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 12. Relative linearity is used to determine actual change in vo ltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 13. MI = RTOT / 255 or (R H - RL) / 255, single pot. 14. During power-up, V CC > VH, VL, and VW. Symbol Parameter Limits Test Conditions Min. (Note 18) Typ. Max. (Note 18) Units RTOTAL End to End Resistance 100 k Ω T version RTOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW +25 °C, each pot IW Wiper Current ±3 mA RW Wiper Resistance 300 WI W = ± 3mA @ VCC = 3V RW Wiper Resistance 150 WI W = ± 3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin VSS VCC VV SS = 0V Noise -120 dBV /√Hz Ref: 1V Resolution 0.4 % Absolute Linearity (Note 11) ±1 MI (Note 13) Rw(n)(actual) - Rw(n)(expected) (Note 15) Relative Linearity (Note 12) ±0.2 MI (Note 13) Rw(n + 1) - [Rw(n) + MI] (Note 15) Temperature Coefficient of RTOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitance 10/10/25 pF See macro model RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (VCC) Limits (Note 14) X9271 5V ± 10% X9271-2.7 2.7V to 5.5V X9271
15 FN8174.3 June 23, 2011 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS NOTES: 16. This parameter is not 100% tested. 17. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and are not 100% tested. 18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Symbol Parameter Limits Test Conditions Min. (Note 18) Typ. Max. (Note 18) Units ICC1 VCC Supply Current (Active) 400 μAf SCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC2 VCC Supply Current (Nonvolatile Write) 15 m A f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ISB VCC Current (Standby) 3 μAS C K = S I = VSS, Addr. = VSS, CS = VCC = 6V ILI Input Leakage Current 10 μAV IN = VSS to VCC ILO Output Leakage Current 10 μAV OUT = VSS to VCC VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage 0.4 V I OL = 3mA VOH Output HIGH Voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOH Output HIGH Voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. (Note 18) Units Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 Years Symbol Test Max. (Note 18) Units Test Conditions CIN/OUT (Note 16) Input / Output Capacitance (SI) 8 pF V OUT = 0V COUT (Note 16) Output Capacitance (SO) 8 pF V OUT = 0V CIN (Note 16) Input Capacitance (A0, CS , WP, HOLD, and SCK) 6p F V IN = 0V Symbol Parameter Min. (Note 18) Max. (Note 18) Units tr VCC (Note 16) V CC Power-up Rate 0.2 50 V/ms tPUR (Note 17) Power-up to Initiation of Read Operation 1 ms tPUW (Note 17) Power-up to Initiation of Write Operation 50 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5 X9271
16 FN8174.3 June 23, 2011 EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCK SSI/SPI Clock Frequency 2.5 MHz tCYC SSI/SPI Clock Cycle Time 500 ns tWH SSI/SPI Clock High Time 200 ns tWL SSI/SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 2 μs tFI SI, SCK, HOLD and CS Input Fall Time 2 μs tDIS SO Output Disable Time 0 250 ns tV SO Output Valid Time 200 ns tHO SO Output Hold Time 0 ns tRO SO Output Rise Time 100 ns tFO SO Output Fall Time 100 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 10 ns tCS CS Deselect Time 2 μs tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel 2714Ω 1382Ω 100pF SO pin 1217Ω X9271
17 FN8174.3 June 23, 2011 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Paramete rT y p . M a x . U n i t s tWR High-voltage Write Cycle Time (Store Instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper Response Time After Third (Last) Power Supply is Stable 5 10 μs tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 5 10 μs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9271
18 FN8174.3 June 23, 2011 TIMING DIAGRAMS Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO X9271
19 FN8174.3 June 23, 2011 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction) X9271
20 FN8174.3 June 23, 2011 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I 3-terminal Potentiometer; Variable Voltage Divider 2-terminal Variable Resistor; Variable Current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9271
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8174.3 June 23, 2011 Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB Frequency ∝ R1, R2, C Amplitude ∝ RA, RB C VO X9271
22 FN8174.3 June 23, 2011 X9271 Package Outline Drawing M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40
0.20 C B A
0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW