X9271TVI-2.7

X9271 XICOR | Alldatasheet

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REV 1.1.7 2/6/03 Characteristics subject to change without notice. 1 of 23 www.xicor.com X9271 Single Digitally-Controlled (XDCP TM ) Potentiometer

FEATURES

• 256 Resistor Taps
• SPI Serial Interface for write, read, and transfer operations of the potentiometer
• Wiper Resistance, 100 Ω typical @ V CC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 3µA Max CC : 2.7V to 5.5V Operation
• 50K Ω , 100K Ω versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale Package)
• Low Power CMOS

DESCRIPTION

The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 256-tap / SPI bus A PPLICATION N OTES AND D EVELOPMENT S YSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM 50KΩ and 100KΩ RH RLRW POT VCC VSS SPI Bus Power On Recall Wiper Counter Register (WCR) Data Registers

16 Bytes

Characteristics subject to change without notice. 2 of 23REV 1.1.7 2/6/03 www.xicor.com DETAILED FUNCTIONAL DIAGRAM R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW INTERFACE AND CONTROL CIRCUITRY VCC VSS Bank 0 R0 R1 R2 R3 Bank 1 R0 R1 R2 R3 Bank 2 R0 R1 R2 R3 Bank 3 12 additional nonvolatile registers

3 Banks of 4 registers x 8-bits

50KΩ and 100KΩ Power On Recall CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

Characteristics subject to change without notice. 3 of 23REV 1.1.7 2/6/03 www.xicor.com PIN CONFIGURATION PIN ASSIGNMENTS TSSOP CSP Symbol Function 1 B3 SO Serial Data Output. 2 A4 A0 Device Address. 3 B2, C2, C3 NC No Connect. 4B 4 C S Chip Select. 5 C4 SCK Serial Clock. 6 D4 SI Serial Data Input. 7D 3 V SS System Ground. 8D 2 W P Hardware Write Protect. 9 D1 A1 Device Address. 10 C1 HOLD Device select. Pause the serial bus.

11 B1 R

W Wiper Terminal of the Potentiometer.

12 A1 R

H High Terminal of the Potentiometer.

13 A2 R

L Low Terminal of the Potentiometer.

14 A3 V

System Supply Voltage. VCC RL VSS 7 8 RW SCK CS TSSOP RH X9271 NC SI HOLD WP A0 V CC RL RH CS SO NC R W SCK NC NC HOLD SI V SS WP A1 A B C D 4321

Characteristics subject to change without notice. 4 of 23REV 1.1.7 2/6/03 www.xicor.com PIN DESCRIPTIONS Bus Interface Pins S ERIAL O UTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. S ERIAL I NPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. S ERIAL C LOCK (SCK) The SCK input is used to clock data into and out of the X9271. H OLD (HOLD) HOLD is used in conjunction with the CS pin to select the de vice. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. D EVICE A DDRESS (A1 - A0) The address inputs are used to set the the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. C HIP S ELECT (CS) When CS is HIGH, the X9271 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins R H , R L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. R W The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins S YSTEM S UPPLY V OLTAGE CC AND S UPPLY G ROUND SS The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins H ARDWARE W RITE P ROTECT I NPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. N O C ONNECT No connect pins should be left floating. This pins are used for Xicor manufacturing and testing purposes.

Characteristics subject to change without notice. during the entire operation. switch may be turned on at a time. Figure 1. Detailed Potentiometer Block Diagram

at a time by the Increment/ Decrement instruction. Register zero (DR0) upon power-up. of Bank 0 is the default value. parameters or user preference data. WIP: Write In Progress status bit, read only. Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV). Table 3. Status Register, SR (WIP is 1-bit)

I DENTIFICATION BYTE (ID AND A) The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9271; this is fixed as 0101[B] (refer to Table 4). The A1-A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A1-A0 input pins. The slave address is externally specified by the user. The X9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9271 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1-A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS. INSTRUCTION BYTE (I[3:0]) The next byte sent to the X9271 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9271 is single POT, the P0=0. The format is shown in Table 5. R EGISTER BANK SELECTION (R1, R0, P1, P0) There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for data register to Wiper Counter Register operations. Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for SPI write and read operations. The data registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. Register Selection (DR0 to DR3) Table Register Bank Selection (Bank 0 to Bank 3) Table RB RA Register Selection Operations 0 0 0 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Data Register Read and Write; Wiper Counter Register Operations 1 0 2 Data Register Read and Write; Wiper Counter Register Operations 1 1 3 Data Register Read and Write; Wiper Counter Register Operations P1 P0 Bank Selection Operations 0 0 0 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Data Register Read and Write Only 1 0 2 Data Register Read and Write Only 1 1 3 Data Register Read and Write OnlyTable 4. Identification Byte Format ID3 ID2 ID1 ID0 0 0 A1 A0 0101 (MSB) (LSB) Device Type Identifier Set to 0 for proper operation Internal Slave Address

Table 5. Instruction Byte Format Five of the eight instructions are three bytes in length. instruction is the only unique format (see Figure 4). Register to the associated Wiper Counter Register. thereby, providing a fine tuning capability to the host. See Instruction format for more details. WIP bit is read with a Read Status command.

Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Wiper Position (Sent by X9271 on SO) CS Rising Edge010100 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge010100 A 1 A 0 10100000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge01010 0 A 1 A 0 1 0 1 1 R B R A P 1 P 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE

010100 A 1 A 0 1100 R B R A P 1 P 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

01010 0 A 1 A 0 1110R B R A 0 0

Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Read Status Register (SR) Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WCRx refers to wiper position data in the Wiper Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). (4) “X:”: Don’t Care. CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge01010 0A 1A 01 1 0 1 R B R A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) CS Rising Edge010100A 1A 0 0010XX00I / DI / D .... I / D I / D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge01010 0A 1A 00 1 0100010000000 W I P

Voltage on SCK any address input COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC)(4) Limits X9271 5V ±10% X9271-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH – RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k Ω T version RTOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 °C, each pot IW Wiper Current ±3 mA RW Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V RW Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV / Hz Ref: 1V Resolution 0.4 % Absolute Linearity(1) ±1 MI (3) Rw(n)(actual) – Rw(n)(expected) (5) Relative Linearity(2) ±0.2 MI (3) Rw(n + 1) – Rw(n) + MI Temperature Coefficient of RTOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitancies 10/10/25 pF See Macro model

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) t PUR and t PUW are the delays required from the time the (last) power supply (V CC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 µAf SCK = 2.5 MHz, SO = Open, VCC=6V Other Inputs = VSS ICC2 VCC supply current (nonvolatile write) 1 5 mA f SCK = 2.5MHz, SO = Open, VCC=6V Other Inputs = VSS ISB VCC current (standby) 3 µA SCK = SI = V SS, Addr. = VSS, CS = VCC = 6V ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage –1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOH Output HIGH voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions CIN/OUT (6) Input / Output capacitance (SI) 8 pF V OUT = 0V COUT (6) Output capacitance (SO) 8 pF V OUT = 0V CIN (6) Input capacitance (A0, CS, WP, HOLD, and SCK) 6p F V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC Power-up rate 0.2 50 V/ms tPUR (7) Power-up to initiation of read operation 1 ms tPUW (7) Power-up to initiation of write operation 50 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5

EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCK SSI/SPI clock frequency 2.5 MHz tCYC SSI/SPI clock cycle time 500 ns tWH SSI/SPI clock high time 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 250 ns tV SO output valid time 200 ns tHO SO output hold time 0 ns tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns tCS CS deselect time 2 µs tWPASU WP, A0 setup time 0 ns tWPAH WP, A0 hold time 0 ns 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel 2714Ω 1382Ω 100pF SO pin 1217Ω

HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO

XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction)

Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R2R1

Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0∞ – 8∞ .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Ball Matrix: 4321 A A0 Vcc RL RH B CS SO NC RW C SCK NC NC HOLD D SI Vss WP A1 Package Dimensions Symbol Millimeters Min Nominal Max Package Width a 2.593 2.623 2.653 Package Length b 2.771 2.801 2.831 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.200 0.220 0.240 Ball Diameter f 0.300 0.320 0.340 Ball Pitch – Width j 0.5 Ball Pitch – Length k 0.5 Ball to Edge Spacing – Width l 0.537 0.562 0.587 Ball to Edge Spacing – Length m 0.626 0.651 0.676 9271TRR YWW I LOT # 16-Bump Chip Scale Package (CSP B16) Package Outline Drawing f m j l k b a d e e c Top View (Marking Side) Bottom View (Bumped Side) Side View Side View A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1

Characteristics subject to change without notice. 23 of 23 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2003 Patents Pending REV 1.1.7 2/6/03 www.xicor.com

ORDERING INFORMATION

Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package V = 14-Lead TSSOP B = 16-Lead CSP Potentiometer Organization Pot U = 50K Ω T = 100K Ω X9271 V T V Y