X9269TV24-2.7

X9269 XICOR | Alldatasheet

Document overview

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Technical content

REV 1.1.11 2/17/03 Characteristics subject to change without notice. 1 of 25 www.xicor.com X9269 Dual Digitally-Controlled (XDCP TM ) Potentiometers

FEATURES

• Dual–Two separate potentiometers
• 256 resistor taps/pot–0.4% resolution
• 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer single supply device Wiper Resistance, 100 Ω typical V CC = 5V
• 4 Nonvolatile Data Registers for Each Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 5µA Max
• 50K Ω , 100K Ω versions of End to End Pot Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 24-Lead SOIC, 16-Lead CSP (Chip Scale Pack- age), 24-Lead TSSOP
• Low Power CMOS
• Power Supply V CC = 2.7V to 5.5V

DESCRIPTION

The X9269 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 256-tap / 2-Wire bus A PPLICATION N OTES AND D EVELOPMENT S YSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM RH0 RL0RW0 VCC VSS 2-Wire Bus 50KΩ or 100KΩ versions RH1 RL1RW1 Power On Recall Wiper Counter Registers (WCR) Data Registers (DR0–DR3) Interface Bus Interface and Control Address Data Status Write Read Transfer Inc/Dec Control

REV 1.1.11 2/17/03 Characteristics subject to change without notice. 2 of 25 www.xicor.com DETAILED FUNCTIONAL DIAGRAM INTERFACE AND CONTROL CIRCUITRY SCL SDA WP VCC VSS R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 R0 R1 R2 R3 Wiper Counter Register (WCR) Data Pot 0 Power On Recall Power On Recall RH0 RL0 RW0 RH1RL1 RW1 256-taps 50KΩ and 100KΩ CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

REV 1.1.11 2/17/03 Characteristics subject to change without notice. 3 of 25 www.xicor.com PIN CONFIGURATION PIN ASSIGNMENTS Pin (SOIC/TSSOP) Pin (CSP) Symbol Function

1 C2 NC No Connect

2 D2 A0 Device Address for 2-Wire bus.

3 N/A NC No Connect

4 N/A NC No Connect

5 N/A NC No Connect

6 N/A NC No Connect

Low Terminal for Potentiometer 0. 9A 1 R High Terminal for Potentiometer 0.

10 B1 R

Wiper Terminal for Potentiometer 0. 11 A2 A2 Device Address for 2-Wire bus.

12 B2 WP

13 B3 SDA Serial Data Input/Output for 2-Wire bus. 14 A3 A1 Device Address for 2-Wire bus.

15 B4 R

Low Terminal for Potentiometer 1.

16 A4 R

High Terminal for Potentiometer 1.

17 C4 R

Wiper Terminal for Potentiometer 1.

18 D4 V

19 N/A NC No Connect

20 N/A NC No Connect

21 N/A NC No Connect

22 N/A NC No Connect

23 D3 SCL Serial Clock for 2-Wire bus. 24 C3 A3 Device Address for 2-Wire bus. NC NC NC VCC RL0 SCL NC NC NC NC VSS RW1 RH1 RL1 SOIC/TSSOP X9269 NC NC RH0 RW0 A2 A1 SDAWP CSP 2 3 4 A B C D Top View–Bumps Down RH0 A2 A1 R H1 RW0 WP SDA R L1 RL0 NC A3 R W1 VCC A0 SCL V SS

REV 1.1.11 2/17/03 Characteristics subject to change without notice. 4 of 25 www.xicor.com PIN DESCRIPTIONS Bus Interface Pins S ERIAL D ATA I NPUT UTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. S ERIAL C LOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9269. D EVICE A DDRESS (A3–A0) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9269. A maximum of 16 devices may occupy the 2-Wire serial bus. Potentiometer Pins R H , R L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of R H and R L such that R and R are the terminals of POT 0 and so on. R W The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 2 sets of R W such that R is the terminal of POT 0 and so on. Bias Supply Pins S YSTEM S UPPLY V OLTAGE CC AND S UPPLY G ROUND SS The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins N O C ONNECT No connect pins should be left open. This pins are used for Xicor manufacturing and testing purposes. H ARDWARE W RITE P ROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers.

– Instruction and Register Description. switch may be turned on at a time. Power Up and Down Requirements. Figure 1. Detailed Potentiometer Block Diagram

slave device in all applications. not respond to any command until this condition is met. while SCL is HIGH. See Figure 2. byte the X9269 will respond with a final acknowledge. Figure 2. Acknowledge Response from Receiver

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9269 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9269 is still busy with the write operation no ACK will be returned. If the X9269 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. FLOW 1: ACK Polling Sequence INSTRUCTION AND REGISTER DESCRIPTION Instructions D EVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9269 from the host is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9269; this is fixed as 0101[B] (refer to Table 1). The A[3:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A3-A0 input pins. The slave address is externally specified by the user. The X9269 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9269 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3-A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS. INSTRUCTION BYTE (I) The next byte sent to the X9269 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four Data Registers of each associated XDCP . The least significant bit points to one of two Wiper Counter Registers or Pots. The format is shown in Table 2. Register Selection Nonvolatile Write Command Completed EnterACK Polling Issue START Issue Slave Address ACK Returned? Further Operation? Issue Instruction Issue STOP No Yes Yes Proceed Issue STOP No Proceed Register Selected RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1

Table 1. Identification Byte Format Table 2. Instruction Byte Format Table 3. Instruction Set

instruction (see Instruction section for more details). Register zero (DR0) upon power-up. parameters or user preference data. Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Four of the nine instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9269; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Reg- isters. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 6). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9269 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (t HIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the R H terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the R L terminal. See Instruction format for more details.

Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K Wiper Position (Sent by X9269 on SDA) M A C K S T O P0 1 0 1 A 3A 2A 1A 0 1 0 0 1 0 0 0 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P0 1 0 1 A 3A 2A 1A 0 1 0 1 0 0 0 0 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K Wiper Position (Sent by X9269 on SDA) M A C K S T O P0 1 0 1 A 3A 2A 1A 0 1 0 1 1R BR A 0 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0101A 3 A 2 A 1 A 0 1100 R B R A0 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K S T O P0101 A 3 A 2 A 1 A 0 0001R BR A 0 0

Global XFR Wiper Counter Register (WCR) to Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high). S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE

0101 A 3 A 2 A 1 A 0 1000R B R A00

S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE

0101 A 3 A 2 A 1 A 0 1110 R B R A 0 P 0

S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K S T O P0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA 0 P0 S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/WCR Addresses S A C K Increment/Decrement (Sent by Master on SDA) S T O P0101 A 3 A 2 A 1 A 0 001000 0 P 0 I / D I / D .... I / D I / D

Voltage on SCL, SDA any address input COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC)(4) Limits X9269 5V ±10% X9269-2.7 2.7V to 5.5V POTENTIOMETER CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH – RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k Ω T version RTOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 °C, each pot IW Wiper Current ±3 mA RW Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V RW Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV Ref: 1V Resolution 0.4 % Absolute Linearity (1) ±1 MI (3) Rw(n)(actual) – Rw(n)(expected) (5) Relative Linearity (2) ±0.6 MI (3) Rw(n + 1) – Rw(n) + MI Temperature Coefficient of RTOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitances 10/10/25 pF See Macro model Ial RW, RH, RL Leakage 0.1 10.0 µA Device in stand by. Vin = VSS to VCC

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of V CC and the voltages applied to the poten- tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up timing spec is always in effect. A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) t PUR and t PUW are the delays required from the time the (last) power supply (V CC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 µA f SCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and ICC2 VCC supply current (nonvolatile write) 1 5 mA f SCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) ISB VCC current (standby) 5 µAV CC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage –1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOH Output HIGH voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions CIN/OUT (6) Input / Output capacitance (SDA) 8 pF V OUT = 0V CIN (6) Input capacitance (SCL, WP, A3, A2, A1 and A0) 6 pF V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC Power-up rate 0.2 50 V/ms tPUR (7) Power-up to initiation of read operation 1 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5

EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns TI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1, A2, A3 Setup Time 0 ns tHD:WPA A0, A1, A2, A3 Hold Time 0 ns 1533Ω 100pF SDA pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel3V 867Ω 100pF SDA pin

HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA

XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing SCL SDA VWx (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (Any Instruction)

Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R2R1 10KΩ 10KΩ VCC

Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO

Ball Matrix: 432 1 A RH1 A1 A2 RH0 B RL1 SDA WP RW0 C RW1 A3 NC RL0 D Vss SCL A0 Vcc Package Dimensions Symbol Millimeters Inches Min Nominal Max Min Nominal Max Package Width a 2.745 2.775 2.805 Package Length b 4.523 4.553 4.583 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.200 0.220 0.240 Ball Diameter f 0.300 0.320 0.340 Ball Pitch – Width j 0.65 Ball Pitch – Length k 0.65 Ball to Edge Spacing – Width l 0.388 0.413 0.438 Ball to Edge Spacing – Length m 1.277 1.302 1.327 f b a A4 A3 A2 A1 e d 16-Bump Chip Scale Package (CSP B16) Package Outline Drawing Side View j m l k Top View (Marking Side) Bottom View (Bumped Side) Side View e c B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 9269TRR YWW I LOT #

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP, Package Code V24 .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) 0.002 (0.05) 0.005 (0.15) .041 (1.05) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16)(7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0°–8°

0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° – 8° X 45°

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2003 Patents Pending

ORDERING INFORMATION

Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S24 = 24-Lead SOIC B16 = 16-Lead CSP V24 = 24-Lead TSSOP Potentiometer Organization Pot U = 50K Ω T = 100K Ω X9269 P T V Y