X9261UV24Z

X9261 RENESAS | Alldatasheet

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Technical content

FN8171.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9261 Single Supply/Low Power/256-Tap/SPI Bus Dual Digitally-Controlled (XDCP™) Potentiometers

FEATURES

• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiometer Single Supply Device
• Wiper Resistance, 100 typical @ V CC = 5V
• 4 Nonvolatile Data Registers for Each Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall Loads Saved Wiper Position on Power-up.
• Standby Current < 5µA Max
• 5 0 k, 100k Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 24 Ld SOIC, 24 Ld TSSOP
• Low Power CMOS
• Power Supply V CC = 5V ±10%
• Pb-Free Plus Anneal Available (RoHS Compliant)

DESCRIPTION

The X9261 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled poten tiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switch es. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM RH0 RL0 Bus RW0 Interface and Control VCC VSS SPI Bus Address Data Status Write Read Transfer 50k or 100k versions Inc/Dec RH1 RL1RW1 Power-on Recall Wiper Counter Register (WCR) Data Registers (DR0-DR3) Interface Control Data Sheet October 12, 2006OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT ISL22424

2 FN8171.4 October 12, 2006 DETAILED FUNCTIONAL DIAGRAM CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits

Ordering Information

(V) R TOTAL (k) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9261US24 X9261US 5 ±10% 50 0 to 70 24 Ld SOIC (300 mil) M24.3 X9261US24Z (Note) X9261US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9261UV24 X9261UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9261UV24Z (Note) X9261UV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 RH1RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) RH0 RL0 Data RW0 RW1 Pot 0 INTERFACE AND CONTROL CIRCUITRY VCC VSS 256-taps 50k and 100k CS SCK SO SI HOLD WP Power-on Recall Power-on Recall X9261

3 FN8171.4 October 12, 2006 SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wire- less systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems PIN CONFIGURATION PIN ASSIGNMENTS PIN DESCRIPTIONS Bus Interface Pins S ERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. S ERIAL INPUT SI is the serial data inpu t pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. S ERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9261. SO NC NC VCC RL0 HOLD SCK NC NC NC NC V SS RW1 RH1 RL1 SOIC/TSSOP X9261 NC NC RH0 RW0 CS A1 SIWP Pin (SOIC/ TSSOP) Symbol Function

1 SO Serial Data Output for SPI bus

2 A0 Device Address for SPI bus. 3 NC No Connect. 4 NC No Connect. 5 NC No Connect. 6 NC No Connect. CC System Supply Voltage 8R L0 Low Terminal for Potentiometer 0. 9R H0 High Terminal for Potentiometer 0. 10 R W0 Wiper Terminal for Potentiometer 0. 11 CS Device Address for SPI bus.

12 WP Hardware Write Protect

13 SI Serial Data Input for SPI bus

14 A1 Device Address for SPI bus. 15 R L1 Low Terminal for Potentiometer 1. 16 R H1 High Terminal for Potentiometer 1. 17 R W1 Wiper Terminal for Potentiometer 1.

18 V SS System Ground

19 NC No Connect

20 NC No Connect

21 NC No Connect

22 NC No Connect

23 SCK Serial Clock for SPI bus

24 HOLD

Device select. Pause the SPI serial bus. X9261

4 FN8171.4 October 12, 2006 HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the 4-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9261. C HIP SELECT (CS) When CS is HIGH, the X9261 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9261, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins R H, RL The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of R W such that RW0 is the terminals of POT 0 and so on. Supply Pins S YSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins NO CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. PRINCIPLES OF OPERATION Serial Interface The X9261 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9261 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer H and RL inputs). At both ends of each arra y and between each resistor segment is a CMOS switch connected to the wiper W) output. Within each individual array only one switch may be turned on at a time. These switches are cont rolled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). Power-up and Down Requirements. There are no restrictions on the power-up or power- down conditions of V CC and the voltages applied to the potentiometer pins provided that V CC is always more positive than or equal to V H, V L, and V W, i.e., VCC, VH, VL, VW. The V CC ramp rate specification is always in effect. X9261

Figure 1. Detailed Potentiometer Block Diagram instruction (See Instructio n section for more details). Register zero (DR0) upon power-up. different from the value present at power-down. proper loadings of the DR0 value into the WCR. parameters or user preference data. WIP: Write In Progress status bit, read only.

Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Registers or Pots.The format is shown below in Table 4. Table 3. Identification Byte Format Table 4. Instruction Byte Format

7 FN8171.4 October 12, 2006 Register Selection DEVICE DESCRIPTION Instructions Four of the ten instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. – Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the th ree byte instructions is illustrated in Figure 3. Th ese three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper positio n. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonv olatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9261; ei ther between the host and one of the data registers or directly between the host and the Wiper Counter Regi ster. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all speci- fied Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9261 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuni ng capability to the host. For each SCL clock pulse (t HIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the R H terminal. Similarly, for each SCL clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the R L terminal. A detailed illustration of the sequence and timing for this operation are shown. See In struction format for more details. Register Selected RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 X9261

Table 5. Instruction Set

11 FN8171.4 October 12, 2006 Write Data Register (DR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Read Status Register (SR) Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01100R B R A 0 P 0 D D D D D D D D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR Addresses CS Rising Edge010100 A 1 A 0 0001 R B R A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01000R B R A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01110R BR A0P 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses CS Rising Edge0 1 0 100A 1A 01101R BR A0P 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Increment/Decrement (Sent by Master on SDA) CS Rising Edge0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Data Byte (Sent by X9261 on SO) CS Rising Edge0 1 0 100A 1A 0010100010000000 W I P X9261

12 FN8171.4 October 12, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on SCK any address input COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. POTENTIOMETER CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up V CC > VH, VL, and VW. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k  T version RTOTAL End to End Resistance 50 k  U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 C, each pot I W Wiper Current ±3 mA RW Wiper Resistance 300  IW = 3mA @ V+ = 3V RW Wiper Resistance 150  IW = 3mA @ V+ = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV Ref: 1V Resolution 0.4 % Absolute Linearity (1) ±1 MI (3) Rw(n)(actual) - Rw(n)(expected)(5) Relative Linearity (2) ±0.6 MI (3) Rw(n + 1) - Rw(n) + MI Temperature Coefficient of RTOTAL 300 ppm/ C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitances 10/10/25 pF See Macro model Ial RW, RH, RL Leakage 0.1 10.0 µA Device in stand by. Vin = VSS to VCC RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 C+ 7 0 C Industrial -40 C+ 8 5 C Device Supply Voltage (V CC)(4) Limits X9261 5V 10% X9261

13 FN8171.4 October 12, 2006 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of V CC and the voltages applied to the poten- tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC  VH, VL, VW. The VCC power-up timing spec is always in effect. A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 Af SCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC2 VCC supply current (nonvolatile write) 15 m A f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ISB VCC current (standby) 5 AS C K = S I = VSS, Addr. = VSS, CS = VCC = 6V ILI Input leakage current 10 AV IN = VSS to VCC ILO Output leakage current 10 AV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage -1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage V CC - 0.8 V I OH = -1mA, VCC  +3V VOH Output HIGH voltage V CC - 0.4 V I OH = -0.4mA, VCC  +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions COUT(6) Output capacitance (SO) 8 pF V OUT = 0V CIN(6) Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK) 6 pF V IN = 0V Symbol Parameter Min. Max. Units tr VCC(6) VCC Power-up rate 0.2 50 V/ms tPUR(7) Power-up to initiation of read operation 1 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X9261

14 FN8171.4 October 12, 2006 EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCK SSI/SPI clock frequency 2 MHz tCYC SSI/SPI clock cycle rime 500 ns tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 s tFI SI, SCK, HOLD and CS input fall time 2 s tDIS SO output disable time 0 250 ns tV SO output valid time 200 ns tHO SO output hold time 0 ns tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns tCS CS deselect time 2 s tWPASU WP, A0, A1 setup time 0 ns tWPAH WP, A0, A1 hold time 0 ns RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel5V 1462 100pF SO pin 2714 1382 100pF SO pin 1217 X9261

15 FN8171.4 October 12, 2006 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE TIMING DIAGRAMS Input Timing Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 s tWRL Wiper response time after instruction issued (all load instructions) 5 10 s WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH X9261

16 FN8171.4 October 12, 2006 Output Timing Hold Timing XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction) X9261

17 FN8171.4 October 12, 2006 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Co mparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100k 10k10k 10k -12V+12V TL072 –VS VO R2R1 X9261

18 FN8171.4 October 12, 2006 Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2  G  +1/2 GO = 1 + R2/R1 fc = 1/(2RC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10k VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency  R1, R2, C amplitude  RA, RB C VO X9261

19 FN8171.4 October 12, 2006 X9261 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 4 2 4 7  0° 8° 0° 8° - Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8171.4 October 12, 2006 X9261 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE Rev. E 12/02 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.