X9251US24Z-2.7

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Document overview

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• PDF pages: 21

Technical content

Features

• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI serial interface for write, read, and transfer operations of the potentiometer
• Wiper resistance: 100 Ω typical at V CC = 5V
• 4 Nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max CC: 2.7V to 5.5V operation
• 50k Ω version of total resistance
• 100 year data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• L o w p o w e r C M O S
• Pb-free (RoHS compliant) POWER UP, INTERFACE CONTROL AND VCC VSS SPI RH0 RL0 DCP0 RW0 SO SI CS HOLD SCK WP WCR0 DR00 DR01 DR02 DR03 RH1 RL1 DCP1 RW1 WCR1 DR10 DR11 DR12 DR13 RH2 RL2 DCP2 RW2 WCR2 DR20 DR21 DR22 DR23 RH3 RL3 DCP3 RW3 WCR3 DR30 DR31 DR32 DR33 Interface STATUS

FIGURE 1. FUNCTIONAL DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 FN8166.6 December 3, 2014 Submit Document Feedback Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC refe rence voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wh eatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

3 FN8166.6 December 3, 2014 Submit Document Feedback Pin Configuration X9251 (24 LD SOIC/TSSOP) TOP VIEW

Ordering Information

PART NUMBER (Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # X9251US24Z (Note 1) X9251US Z 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251US24IZ (Note 1) X9251US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251UV24Z X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) M24.173 X9251UV24IZ X9251UV ZI -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9251US24IZ-2.7 (Note 1 ) X9251US ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251US24Z-2.7 (Note 1) X9251US ZG 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251UV24Z-2.7 X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) M24.173 X9251UV24IZ-2.7 (Note 1) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) M24.173 NOTES: 1. Add "T1" suffix for tape and reel. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9251 . For more information on MSL, please see tech brief TB363 SO RW3 NC VCC RL0 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 X9251 RH3 R RH0 RW0 CS A1 SIWP Pin Descriptions PIN (SOIC) SYMBOL FUNCTION

1 SO Serial Data Output for SPI bus

2 A0 Device Address for SPI bus (see Note 4)

3R W3 Wiper Terminal of DCP3 4R H3 High Terminal of DCP3 5R L3 Low Terminal of DCP3 7V CC System Supply Voltage 8R L0 Low Terminal of DCP0 9R H0 High Terminal of DCP0

10 R W0 Wiper Terminal of DCP0

11 CS SPI bus. Chip Select active low input

12 WP Hardware Write Protect - active low

13 SI Serial Data Input for SPI bus

14 A1 Device Address for SPI bus (see Note 4)

15 R L1 Low Terminal of DCP1

16 R H1 High Terminal of DCP1

17 R W1 Wiper Terminal of DCP1

18 V SS System Ground

20 R W2 Wiper Terminal of DCP2

21 R H2 High Terminal of DCP2

22 R L2 Low Terminal of DCP2

23 SCK Serial Clock for SPI bus

24 HOLD Device select. Pauses the SPI serial bus. 6, 19 NC No Connect NOTE: 4. A0 and A1 device address pins must be tied to a logic level.

4 FN8166.6 December 3, 2014 Submit Document Feedback Functional Pin Descriptions Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9251. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 AND A0) The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1 and A0 must be tied to a logic level which specifies the internal address of the device, see Figures 3 , 4, 5, 6 and 7. CHIP SELECT (CS) When CS is HIGH, the X9251 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS LOW enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. RW The wiper pins are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminals of DCP0 and so on. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left floating. These pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin, when LOW, prevents nonvolatile writes to the Data Registers. Principles of Operation The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer H and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR).

specification is always in effect. zero (DR#0) upon power-up (see Figure 2). proper loadings of the DR#0 value into the WCR#. Each of the four DCPs has four 8-bit nonvolatile Data Registers. memory locations for system parameters or user preference data. This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only.

• WIP = 1, indicates that high-voltage write cycle is in progress.
• WIP = 0, indicates that no high-voltage write cycle is in progress. SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#0 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER INC/DEC LOGIC UP/DN CLK MODIFIED SCK UP/DN 8 8 COUNTER IF WCR = 00[H] then RW is closest to RL IF WCR = FF[H] then RW is closest to RH WIPER (WCR#) #: 0, 1, 2, or 3 DR#2 DR#1 DR#3 - - - DECODE DCP CORE RW RH RL

FIGURE 2. DETAILED POTENTIOMETER BLOCK DIAGRAM TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE) TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE)

HIGH during the entire operation. three-state outputs. This can help to reduce system pin count. TABLE 3. IDENTIFICATION BYTE FORMAT

010100 P i n A 1

TABLE 4. INSTRUCTION BYTE FORMAT TABLE 5. INSTRUCTION SET

• Read Wiper Counter Register – read the current wiper position of the selected potentiometer
• Write Wiper Counter Register – change current wiper position of the selected potentiometer
• Read Data Register – read the contents of the selected Data Register
• Write Data Register – write a new value to the selected Data Register
• Read Status – this command returns the contents of the WIP bit which indicates if the internal write cycle is in progress The basic sequence of the three-byte instructions is illustrated in

Figure 4. These three-byte instructions exchange data between nonvolatile memory and takes a minimum of tWR to complete.

• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.
• Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. Increment/Decrement Command The final command is Increment/Decrement (see Figures 7 and 8). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9251 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps, thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one wiper position towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See “Instruction Format” on page 10 for more details. XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the conten ts of the Wiper Counter Register pointed to by P1, P0 to the Data Register pointed to by RB, RA Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by RB, RA of all four pots to their respective Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB, RA of all four pots Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch pointed to by P1, P0 NOTE: 1/0 = data is one or zero

TABLE 5. INSTRUCTION SET (Continued)

10 FN8166.6 December 3, 2014 Submit Document Feedback Instruction Format Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES WIPER POSITION (SENT BY X9251 ON SO) CS RISING EDGE0101 0 0 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES DATA BYTE (SENT BY HOST ON SI) CS RISING EDGE010100 A 1 A 010100000 W C R W C R W C R W C R W C R W C R W C R W C R CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES DATA BYTE (SENT BY X9271 ON SO) CS RISING EDGE010100A 1 A 0 1011R BR AP 1 P 0 D D D D D D D D CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES DATA BYTE (SENT BY HOST ON SI) CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D D D D D D D D CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR ADDRESSES CS RISING EDGE 010100A 1A 00 0 0 1R B R A0 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR ADDRESSES CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE 0 1 0 100A 1A 01000R B R A00 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE 0 1 0 100A 1A 01110 R B R A 0 0

11 FN8166.6 December 3, 2014 Submit Document Feedback Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Read Status Register (SR) CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES CS RISING EDGE 0101 0 0A 1A 0 1 1 0 1R B R A 0 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES INCREMENT/DECREMENT (SENT BY MASTER ON SI) CS RISING EDGE010100A 1 A 00010XX00I / DI / D . . . .I / D I / D CS FALLIN G EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES DATA BYTE (SENT BY X9251 ON SO) CS RISING EDGE0 1 0 100A 1A 0010100010 0 0 0000 W I P NOTES: 5. “A1 ~ A0”: stands for the device addresses sent by the master. 6. WPx refers to wiper position data in the Counter Register 7. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). 8. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

12 FN8166.6 December 3, 2014 Submit Document Feedback Absolute Maximum Ratings Rec ommended Operating Conditions Voltage on SCK, CS, SI, SO, WP, HOLD, VCC Supply Voltage (VCC) Limits (Note 12) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. Analog Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RTOTAL End to End Resistance U version 50 k Ω End to End Resistance Tolerance ±20 % RW Wiper Resistance IW = at V CC = 3V 300 Ω IW = at V CC = 5V 220 Ω VTERM Voltage on any RH or RL Pin V SS = 0V V SS VCC V Noise (Note 14) Ref: 1V -120 dBV √Hz Resolution 0.4 % Absolute Linearity (Note 9)R w(n)(actual) - Rw(n)(expected) (Note 13)- 1 + 1 M I (Note 11) Relative Linearity (Note 10)R w(n + 1) - [Rw(n) + MI] (Note 13) -0.6 +0.6 MI (Note 11) Temperature Coefficient of RTOTAL (Note 14) 300 ppm/ C Ratiometric Temp. Coefficient ( Note 14) 20 ppm/°C CH/CL/CW Potentiometer Capacitances See macromodel on page 13, (Note 14) 10/10/25 pF V(VCC) RTOTAL V(VCC) RTOTAL DC Operating Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC Supply Current (Active) f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS 400 µA ICC2 VCC Supply Current (Nonvolatile Write) fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS 15m A ISB VCC Current (Standby) SCK = SI = V SS, Addr. = VSS, CS = VCC = 6V 3µ A ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage V CC x 0.7 V VIL Input LOW Voltage VCC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V VOH Output HIGH Voltage I OH = -1mA, VCC  +3V V CC - 0.8 V VOH Output HIGH Voltage I OH = -0.4mA, VCC  +3V V CC - 0.4 V

13 FN8166.6 December 3, 2014 Submit Document Feedback Equivalent AC Load Circuit Endurance and Data Retention PARAMETER MIN UNITS Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Capacitance SYMBOL TEST TEST CONDITIONS TYP UNITS CIN/OUT (Note 14) Input/Output capacitance (SI) V OUT = 0V 8 pF COUT (Note 14) Output capacitance (SO) V OUT = 0V 8 pF CIN (Note 14) Input capacitance (A0, A1, CS , WP, HOLD, and SCK) V IN = 0V 6 pF Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 14) V CC Power-up Rate 0.2 V/ms tPUR (Note 15) Power-up to Initiation of Read Operation 1 ms tPUW (Note 15) Power-up to Initiation of Write Operation 50 ms AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5 NOTES: 9. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 10. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 11. MI = RTOT/255 or (R H - RL)/255, single pot. 12. During power up V CC > VH, VL, and VW. 14. This parameter is not 100% tested 15. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODELVCC 2kΩ 10pF SO PIN 2kΩ

14 FN8166.6 December 3, 2014 Submit Document Feedback AC TIMING SYMBOL PARAMETER MIN MAX UNITS fSCK SPI clock frequency 2M H z tCYC SPI Clock Cycle Time 500 ns tWH SPI Clock High Time 200 ns tWL SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 2 µs tFI SI, SCK, HOLD and CS Input Fall Time 2 µs tDIS SO Output Disable Time 0 250 ns tV SO Output Valid Time 200 ns tHO SO Output Hold Time 0 ns tRO (Note 14) SO Output Rise Time 100 ns tFO (Note 14) SO Output Fall Time 100 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 10 ns tCS CS Deselect Time 2 µs tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-voltage write cycle time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO (Note 14) Wiper response time after the third (last) power supply is stable 5 10 µs tWRL (Note 14) Wiper response time after instruction issued (all load instructions) 5 10 µs

15 FN8166.6 December 3, 2014 Submit Document Feedback Symbol Table Timing Diagrams Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ... CS SCK SI SO MSB LSB HIGH IMPEDANCE tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ...

16 FN8166.6 December 3, 2014 Submit Document Feedback Hold Timing XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VWx tWRL ... SO HIGH IMPEDANCE CS WP tWPASU tWPAH (ANY INSTRUCTION)

17 FN8166.6 December 3, 2014 Submit Document Feedback Applications information Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current NON INVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS VS VO VO = (1 + R2/R1)VS Iadj VO (REG) = 1.25V (1 + R2/R1) + Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1 + R2)} VO(max) RLL = {R1/(R1 + R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1

18 FN8166.6 December 3, 2014 Submit Document Feedback Application Circuits (continued) ATTENUATOR FILTER INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO VO = G VS -1/2  G  +1/2 GO = 1 + R2/R1 fc = 1/(2RC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB FREQUENCY  R1, R2, C AMPLITUDE RA, RB C VO

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8166.6 December 3, 2014 For additional products, see www.intersil.com/en/products.html Submit Document Feedback About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 3, 2014 FN8166.6 Updated to Intersil new standards. Updated Ordering Information Table on page 3, by removing obsoleted parts and 100kΩ referenced parts, adding Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”. Added Revision History and About Intersil verbiage. Updated M24.3 POD to the latest revision. -“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern.” Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24 Ld version.

20 FN8166.6 December 3, 2014 Submit Document Feedback Package Outline Drawing M24.3

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)

Rev 2, 3/11 TOP VIEW NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. SIDE VIEW “A” SIDE VIEW “B” TYPICAL RECOMMENDED LAND PATTERN INDEX AREA 123 SEATING PLANE DETAIL "A" x 45° 7.60 (0.299) 7.40 (0.291) 0.75 (0.029) 0.25 (0.010) 10.65 (0.419) 10.00 (0.394) 1.27 (0.050) 0.40 (0.016) 15.60 (0.614) 15.20 (0.598) 2.65 (0.104) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.23 (0.009) 1.981 (0.078) 9.373 (0.369)

21 FN8166.6 December 3, 2014 Submit Document Feedback Package Outline Drawing M24.173

24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN TOP VIEW SIDE VIEW END VIEW Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y14.5M-1994. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-153. NOTES: SEATING PLANE C H B 1 3 A PLANE GAUGE

0.05 MIN

0.15 MAX

0°-8° 0.60± 0.15 0.90

1.00 REF

0.25 SEE DETAIL "X" 0.15 0.25 (0.65 TYP) (5.65) (0.35 TYP) (1.45) 6.40 4.40 ±0.10 0.65

1.20 MAX

PIN #1 I.D. MARK 7.80 ±0.10 +0.05 -0.06 -0.06 +0.05 -0.10 +0.15

0.20 C B A

0.10 C - 0.05

0.10 C B AM