X9251US24-2.7

X9251 INTERSIL | Alldatasheet

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Technical content

FN8166.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9251 Single Supply/Low Power/256-Tap/SPI Bus Quad Digitally-Controlled (XDCP™) Potentiometer

FEATURES

• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer operations of the potentiometer
• Wiper resistance: 100Ω typical @ V CC = 5V
• 4 Non-volatile data registers for each potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current < 5µA max CC: 2.7V to 5.5V Operation
• 5 0 kΩ, 100kΩ versions of total resistance
• 100 yr. data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9251 integrates four digitally controlled potentio- meters (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple- mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be di rectly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM POWER UP, INTERFACE CONTROL AND VCC VSS SPI RH0 RL0 DCP0 RW0 SO SI CS HOLD SCK WP WCR0 DR00 DR01 DR02 DR03 RH1 RL1 DCP1 RW1 WCR1 DR10 DR11 DR12 DR13 RH2 RL2 DCP2 RW2 WCR2 DR20 DR21 DR22 DR23 RH3 RL3 DCP3 RW3 WCR3 DR30 DR31 DR32 DR33 Interface STATUS Data Sheet September 14, 2005

2 FN8166.2 September 14, 2005

Ordering Information

PART NUMBER PART MARKING V CC LIMITS (V) POTENTIOMENTER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE X9251UP24I X9251UP I 5 ±10% 50 -40 to +85 24 Ld PDIP X9251US24* X9251US 0 to 70 24 Ld SOIC (300MIL) X9251US24Z* (Note) X9251US Z 0 to 70 24 Ld SOIC (300MIL) (Pb-Free) X9251US24I* X9251US I -40 to +85 24 Ld SOIC (300MIL) X9251US24IZ* (Note) X9251US Z I -40 to +85 24 Ld SOIC (300MIL) (Pb-Free) X9251UV24 X9251UV 0 to 70 24 Ld TSSOP (4.4mm) X9251UV24Z (Note) X9251UV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9251UV24I X9251UV I -40 to +85 24 Ld TSSOP (4.4mm) X9251UV24IZ (Note) X9251UV Z I -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) X9251TP24I 100 -40 to +85 24 Ld PDIP X9251TS24* X9251TS 0 to 70 24 Ld SOIC (300MIL) X9251TS24Z* (Note) X9251TS Z 0 to 70 24 Ld SOIC (300MIL) (Pb-Free) X9251TS24I* X9251TS I -40 to +85 24 Ld SOIC (300MIL) X9251TS24IZ* (Note) X9251TS Z I -40 to +85 24 Ld SOIC (300MIL) (Pb-Free) X9251TV24 X9251TV 0 to 70 24 Ld TSSOP (4.4mm) X9251TV24Z (Note) X9251TV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9251TV24I X9251TV I -40 to +85 24 Ld TSSOP (4.4mm) X9251TV24IZ (Note) X9251TV Z I -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) X9251US24-2.7* X9251US F 2.7 to 5.5 50 0 to 70 24 Ld SOIC (300MIL) X9251US24Z-2.7* (Note) X9251US Z F 0 to 70 24 Ld SOIC (300MIL) (Pb-Free) X9251US24I-2.7* X9251US G -40 to +85 24 Ld SOIC (300MIL) X9251US24IZ-2.7* (Note) X9251US Z G -40 to +85 24 Ld SOIC (300MIL) (Pb-Free) X9251UV24-2.7 X9251UV F 0 to 70 24 Ld TSSOP (4.4mm) X9251UV24Z-2.7 (Note) X9251UV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9251UV24I-2.7 X9251UV G -40 to +85 24 Ld TSSOP (4.4mm) X9251UV24IZ-2.7 (Note) X9251UV Z G -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) X9251TS24-2.7* X9251TS F 100 0 to 70 24 Ld SOIC (300MIL) X9251TS24Z-2.7* (Note) X9251TS Z F 0 to 70 24 Ld SOIC (300MIL) (Pb-Free) X9251TS24I-2.7* X9251TS G -40 to +85 24 Ld SOIC (300MIL) X9251TS24IZ-2.7* (Note) X9251TS Z G -40 to +85 24 Ld SOIC (300MIL) (Pb-Free) X9251TV24-2.7 X9251TV F 0 to 70 24 Ld TSSOP (4.4mm) X9251TV24Z-2.7 (Note) X9251TV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9251TV24I-2.7 X9251TV G -40 to +85 24 Ld TSSOP (4.4mm) X9251TV24IZ-2.7 (Note) X9251TV Z G -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. X9251

3 FN8166.2 September 14, 2005 CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage ampli- fier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wire- less systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems PIN CONFIGURATION PIN ASSIGNMENTS Note 1: A0 - A1 device address pins must be tied to a logic level. Pin (SOIC) Symbol Function

1 SO Serial Data Output for SPI bus

2 A0 Device Address for SPI bus. (See Note 1) 3R W3 Wiper Terminal of DCP3 4R H3 High Terminal of DCP3 5R L3 Low Terminal of DCP3 7V CC System Supply Voltage 8R L0 Low Terminal of DCP0 9R H0 High Terminal of DCP0

10 R W0 Wiper Terminal of DCP0

11 CS SPI bus. Chip Select active low input

12 WP Hardware Write Protect - active low

13 SI Serial Data Input for SPI bus

14 A1 Device Address for SPI bus. (See Note 1) 15 R L1 Low Terminal of DCP1

16 R H1 High Terminal of DCP1

17 R W1 Wiper Terminal of DCP1

18 V SS System Ground

20 R W2 Wiper Terminal of DCP2

21 R H2 High Terminal of DCP2

22 R L2 Low Terminal of DCP2

23 SCK Serial Clock for SPI bus

24 HOLD

Device select. Pauses the SPI serial bus. 6, 19 NC No Connect SO RW3 NC VCC RL0 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 SOIC/TSSOP X9251 RH3 RL3 RH0 RW0 CS A1 SIWP X9251

4 FN8166.2 September 14, 2005 PIN DESCRIPTIONS Bus Interface Pins S ERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. S ERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock. S ERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9251. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SC K is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1 - A0 must be tie to a logic level which specify the internal address of the device, see Figures 2, 3, 4, 5 and 6. C HIP SELECT (CS) When CS is HIGH, the X9251 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS LOW enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R H and RL such that R H0 and RL0 are the terminals of DCP0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of R W such that RW0 is the terminals of DCP0 and so on. Supply Pins S YSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins N O CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. PRINCIPLES OF OPERATION The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR). X9251

Figure 1. Detailed Potentiometer Block Diagram Power Up and Down Recommendations. instruction (See Instructio n section for more details). its contents are lost when the X9251 is powered-down. loadings of the DR#0 value into the WCR#. parameters or user preference data. WIP: Write In Progress status bit, read only.

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile). Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile). during the entire operation. Identification Byte are a Device Type Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3). DCPs.The format is shown below in Table 4. Table 3. Identification Byte Format Table 4. Instruction Byte Format

010100 P i n A 1

Table 5. Instruction Set

8 FN8166.2 September 14, 2005 Instructions Four of the nine instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register, – Write Data Register – write a new value to the selected Data Register, – Read Status – this command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the th ree byte instructions is illustrated in Figure 3. Th ese three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper positio n. The response of the wiper to this action is delayed by t WRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the four potentiometer’s WCR, and one of its associated registers, DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9251; ei ther between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all speci- fied Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9251 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capab ility to the host. For each SCK clock pulse (t HIGH) while SI is HIGH, the selected wiper moves one wiper position towards the R H terminal. Similarly, for each SCK clock pulse while SI is LOW, the sele cted wiper moves one wiper position towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details. X9251

11 FN8166.2 September 14, 2005 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Wiper Position (Sent by X9251 on SO) CS Rising Edge010100 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Data Byte (Sent by Host on SI) CS Rising Edge010100 A 1 A 0 10100000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge010100 A 1 A 0 1011 R B R A P 1 P 0 D D D D D D D D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01100R B R A P 1 P 0 D D D D D D D D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR Addresses CS Rising Edge010100 A 1 A 0 0001 R B R A00 X9251

12 FN8166.2 September 14, 2005 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Read Status Register (SR) Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01000R B R A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100A 1 A 01110R BR A0 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses CS Rising Edge0 1 0 100A 1A 01101R BR A0 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Increment/Decrement (Sent by Master on SI) CS Rising Edge0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode WCR Addresses Data Byte (Sent by X9251 on SO) CS Rising Edge0 1 0 100A 1A 0010100010000000 W I P X9251

13 FN8166.2 September 14, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, any address input, VCC COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k Ω T version RTOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 °C, each pot I W Wiper Current ±3 mA RW Wiper Resistance 300 Ω IW = @ V CC = 3V 150 Ω IW = @ V CC = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV /√Hz Ref: 1V Resolution 0.4 % Absolute Linearity (1) -1 +1 MI (3) Rw(n)(actual) - Rw(n)(expected)(5) Relative Linearity (2) -0.6 +0.6 MI (3) Rw(n + 1) - Rw(n) + MI Temperature Coefficient of RTOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient -20 +20 ppm/°C CH/CL/CW Potentiometer Capacitances 10/10/25 pF See Macro model RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (V CC) Limits(4) X9251 5V ± 10% X9251-2.7 2.7V to 5.5V V(VCC) RTOTAL V(VCC) RTOTAL X9251

14 FN8166.2 September 14, 2005 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 µAf SCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC2 VCC supply current (non-volatile write) 15 m A f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ISB VCC current (standby) 3 µAS C K = S I = VSS, Addr. = VSS, CS = VCC = 6V ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage -1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOH Output HIGH voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions CIN/OUT(6 ) Input / Output capacitance (SI) 8p F VOUT = 0V COUT(6) Output capacitance (SO) 8p F VOUT = 0V CIN(6) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) 6p F VIN = 0V Symbol Parameter Min. Max. Units tr VCC(6) VCC Power-up rate 0.2 50 V/ms tPUR(7) Power-up to initiation of read operation 1 ms tPUW(7) Power-up to initiation of write operation 50 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X9251

15 FN8166.2 September 14, 2005 EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCK SPI clock frequency 2 MHz tCYC SPI clock cycle rime 500 ns tWH SPI clock high rime 200 ns tWL SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 250 ns tV SO output valid time 200 ns tHO SO output hold time 0 ns tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns tCS CS deselect time 2 µs tWPASU WP, A0 setup time 0 ns tWPAH WP, A0 hold time 0 ns RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MacromodelVCC 2kΩ 10pF SO pin 2kΩ X9251

16 FN8166.2 September 14, 2005 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9251

17 FN8166.2 September 14, 2005 TIMING DIAGRAMS Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO X9251

18 FN8166.2 September 14, 2005 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction) X9251

19 FN8166.2 September 14, 2005 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9251

20 FN8166.2 September 14, 2005 Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9251

21 FN8166.2 September 14, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP, Package Code V24 .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0° - 8° X9251

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8166.2 September 14, 2005 PACKAGING INFORMATION 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic, SOIC, Package Code S24 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° - 8° X 45° X9251