X9250TV24I-2.7

X9250 XICOR | Alldatasheet

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Technical content

REV 1.1.5 1/31/03 Characteristics subject to change without notice. 1 of 21 www.xicor.com Low Noise/Low Power/SPI Bus/256 Taps X9250 Quad Digitally Controlled Potentiometers (XDCP

FEATURES

• Four potentiometers in one package
• 256 resistor taps/pot–0.4% resolution
• SPI serial interface
• Wiper resistance, 40 Ω typical @ V CC = 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies CC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V
• 100K Ω , 50K Ω total pot resistance
• High reliability —Endurance – 100,000 data changes per bit per register —Register data retention – 100 years
• 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip Scale Package)
• Dual supply version of X9251

DESCRIPTION

The X9250 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM R 0 R 1 R 2 R 3 Wiper Counter Register (WCR) Resistor Array VH1 /RH1 VL1/RL1 R 0 R 1 R 2 R 3 Wiper Counter Register (WCR) Interface and Control Circuitry CS SCK VH0 /RH0 VL0/RL0 Data VW0 /RW0 VW1 /RW1 SO SI R 0 R 1 R 2 R 3 Wiper Counter Register (WCR) Resistor Array Pot 2 VH2 /RH2 VL2/RL2 VW2 /RW2 R 0 R 1 R 2 R 3 Wiper Counter Register (WCR) Resistor Array Pot 3 VH3 /RH3 VL3/RH3 VW3 /RW3 Pot1 HOLD WP Pot 0 VCC VSS A PPLICATION N OTE A V A I L A B L E AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Characteristics subject to change without notice. 2 of 21REV 1.1.5 1/31/03 www.xicor.com PIN DESCRIPTIONS Serial Output (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9250. Chip Select (CS When CS is HIGH, the X9250 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9250, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A A The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9250. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins V H H ), V L L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. V W W The wiper pins are equivalent to the wiper terminal of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Analog Supplies (V+, V-) The analog supplies V+, V- are the supply voltages for the XDCP analog section. PIN CONFIGURATION VW3 /RW3 VCC VL0/RL0 HOLD SCK VL2/RL2 VH2 /RL2 VW2 /RW2 VSS VW1 /RW1 VH1 /RH1 VL1/RL1 SOIC/TSSOP X9250 VH3 /RH3 VL3/RL3 VH0 /RH0 VW0 /RW0 CS A1 SIWP 2 3 4 A B C D E F Top View–Bumps Down R W0 R L0 HOLD R L1 VCC R L3 RW3 SO SI RW1 SCK R L2 WP RH0 RH1 RH3 RH2 VSS RW2 CS A 1 CSP

The X9250 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9250 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H /RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper W /RW ) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches. Wiper Counter Register (WCR) The X9250 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9250 is powered- down. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. Data Registers Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Data Register Detail Symbol Description SCK Serial Clock SI, SO Serial Data A 0-A1 Device Address VH0 /RH0– VH3 /RH3 , VL0/RL0–VL3/RL3 Potentiometer Pins (terminal equivalent) VW0 /RW0– VW3 /RW3 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection V+,V- Analog Supplies V CC System Supply Voltage VSS System Ground NC No Connection (MSB) (LSB) D7 D6 D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV NV NV

The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P 0) selects which one of the four potentiometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register—This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register— This transfers the contents of all specified Data Reg- isters to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register— This transfers the contents of all Wiper Counter Reg- isters to the specified associated Data Registers. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL . A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9250; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – Read Wiper Counter Register—read the current wiper position of the selected pot, –W rite Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; –W rite Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse HIGH ) while SI is HIGH, the selected wiper will move one resistor segment towards the VH /RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the V L/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence Figure 5. Three-Byte Instruction Sequence (Write) Figure 6. Three-Byte Instruction Sequence (Read) Figure 7. Increment/Decrement Instruction Sequence

010100 A 1 A 0 I3 I2 I1 I0 0 P1 P0

Figure 8. Increment/Decrement Timing Limits Table 1. Instruction Set

1 R 0 P1 P0 Transfer the contents of the Data Register

1 R 0 P1 P0 Transfer the contents of the Wiper Counter

1 R 0 0 0 Transfer the contents of the Data Registers

1000 R 1 R 0 0 0 Transfer the contents of all Wiper Counter

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register(WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge device type identifier device addresses instruction opcode WCR addresses wiper position (sent by X9250 on SO) CS Rising Edge010100 A A 0 100100 P P W P W P W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses Data Byte (sent by Host on SI) CS Rising Edge010100 A A 0 101000 P P W P W P W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by X9250 on SO) CS Rising Edge010100 A A 0 1011 R R P P W P W P W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by host on SI)CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1100 R R P P W P W P W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge010100 A A 0 1101 R R P P

Transfer Wiper Counter Register (WCR) to Data Register (DR) Increment/Decrement Wiper Counter Register (WCR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1110 R R P P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses increment/decrement (sent by master on SI) CS Rising Edge010100 A A 0 0010XX P P 0 I / D I / D .... I / D I / D CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge010100 A A 0 0001 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1000 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode Data Byte (sent by X9250 on SO) CS Rising Edge010100 A A 0 010100010000000 W I P

Voltage on SCK, SCL or any address input Any V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC ) Limits X9250 5V ±10% X9250-2.7 2.7V to 5.5V POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti- ometer. It is a measure of the error in step size. (3) MI = RTOT/255 or (VH /RH –VL/RL)/255, single pot (4) Individual array resolutions. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit End to end resistance tolerance ±20 % Power rating 50 mW 25°C, each pot IW Wiper current ±7.5 mA R W Wiper resistance 150 250 Ω Wiper current = ± 1mA Vv+ Voltage on V+ pin X9250 +4.5 +5.5 V Vv- Voltage on V- pin X9250 -5.5 -4.5 V VTERM Voltage on any VH /RH or VL/RL pin V- V+ V Noise -120 dBV Ref: 1kHz Resolution (4) 0.6 % Absolute linearity (1) ±1 MI (3) Vw(n)(actual)–Vw(n)(expected) Relative linearity (2) ±0.6 MI (3) Vw(n + 1)–[Vw(n) + MI] Temperature coefficient of RTOTAL ±300 ppm/°C Ratiometric Temperature Coefficient ±20 ppm/°C C H /CL/CW Potentiometer Capacitances 10/10/25 pF See Circuit #3

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER UP AND DOWN REQUIREMENT The are no restrictions on the sequencing of the bias supplies VCC , V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The V CC ramp rate spec is always in effect. Notes: (5) This parameter is periodically sampled and not 100% tested (6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC , V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (7) Sample tested only. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit ICC1 VCC supply current (active) 400 µA f SCK = 2MHz, SO = Open, Other Inputs = VSS ICC2 VCC supply current (nonvolatile write) 1m A f SCK = 2MHz, SO = Open, Other Inputs = VSS ISB VCC current (standby) 5 µA SCK = SI = V SS , Addr. = VSS ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 0.1 V VIL Input LOW voltage –0.5 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Symbol Test Max. Unit Test Conditions C OUT (5) Output capacitance (SO) 8 pF V OUT = 0V C IN (5) Input capacitance (A0, A1, SI, and SCK, CS) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tPUR (6) Power-up to initiation of read operation 1 ms tPUW (6) Power-up to initiation of write operation 5 ms tR VCC (7) VCC power up ramp rate 0.2 50 V/msec A.C. TEST CONDITIONS Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5

Symbol Parameter Min. Max. Unit fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle time 500 ns tWH SSI/SPI clock high time 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 75 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable Time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs TBD ns tCS CS deselect time 2 µs tWPASU WP , A0 and A1 setup time 0 ns tWPAH WP , A0 and A1 hold time 0 ns Circuit #3 SPICE Macro Model EQUIVALENT A.C. LOAD CIRCUIT 10pF R H R TOTAL C H 25pF C W C L 10pF R W R L 1533Ω 100pF SDA Output 2.7V 100pF

HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE TIMING DIAGRAMS Input Timing Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Unit tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruc- tion) 40 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH

XDCP Timing (for all Load Instructions) ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance

XDCP Timing (for Increment/Decrement Instruction) Write Protect and Device Address Pins Timing ... CS SCK SO SI ADDR tWRID High Impedance VWx ...Inc/Dec Inc/Dec ... CS WP tWPASU tWPAH (Any Instruction)

Basic Configurations of Electronic Potentiometers Application Circuits VR VW /RW +V R I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO R 2 R 1 VO = (1+R2/R1)VS R 1 R 2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R 2R 1 VUL = {R1/(R1+R 2) VO (max) VLL = {R1/(R1+R 2) VO (min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R 2R 1

Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO R 3 R 1 VO = G VS -1/2 ≤ G ≤ +1/2 G O = 1 + R2/R1 fc = 1/(2πRC) VS VO R 2R 1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS R 2 R 4 R 1 = R2 = R3 = R4 = 10kΩ VS R 2 R 1 R C VO = G VS G = - R2/R1 R 2C 1 R 1 R 3 ZIN – R 2 R 1 R A R B frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO

f j b a d e Top View (Sample Marking) Bottom View (Bumped Side) Side View e A1A4 B4 B3 B1 C4 C1 D4 D2 D1 E4 E2 E1 F1F4 F3 F2 c kl m Side View 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing 9250UA YWW I Lot# Package Dimensions Symbol Millimeters Min Nominal Max Package Width a 2.771 2.801 2.831 Package Length b 4.549 4.579 4.609 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.200 0.220 0.240 Ball Diameter f 0.300 0.320 0.340 Ball Pitch – Width j 0.5 Ball Pitch – Length k 0.5 Ball to Edge Spacing – Width l 0.626 0.651 0.676 Ball to Edge Spacing – Length m 1.015 1.040 1.065 Ball Matrix: 4321 A R L1 A1 CS R W0 B R W1 SI WP R L0 C VSS R H1 R H0 VCC D V- RH2 R H3 V+ E R W2 HOLD SO R L3 F R L2 SCK A0 R W3

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP, Package Code V24 .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16)(7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0°–8°

0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic, SOIC, Package Code S24 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° – 8° X 45°

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2003 Patents Pending

Ordering Information

Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial =0°C to +70°C I = Industrial = –40°C to +85°C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP B24 = 24-Lead CSP Potentiometer Organization T = 100K Ω U= 50K Ω X9250 P T V Y S & V Package Marking Line #1 (Blank) Line #2 (Part Number) Line #3 (Date Code) (*) Line #4 (Blank) = F 2.7V 0 to 70°C G 2.7V -40 to +85°C I 5V -40 to +85 °C