X9241 XICOR | Alldatasheet

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Technical content

Quad E 2POT ™ Nonvolatile Digital Potentiometer © Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 3864-2.7 7/1/96 T0/C3/D3 NS

FEATURES

  • Four E2POTs in One Package
  • Two-Wire Serial Interface
  • Register Oriented Format —Directly Write Wiper Position —Read Wiper Position —Store as Many as Four Positions per Pot
  • Instruction Format —Quick Transfer of Register Contents to Resistor Array —Cascade Resistor Arrays
  • Low Power CMOS
  • Direct Write Cell —Endurance - 100,000 Data Changes per Register —Register Data Retention - 100 years
  • 16 Bytes of E2PROM memory
  • 3 Resistor Array Values —2K Ω to 50KΩ Mask Programmable —Cascadable For Values of 500Ω to 200KΩ
  • Resolution: 64 Taps each Pot
  • 20-Lead Plastic DIP, 20-Lead TSSOP and 20-Lead SOIC Packages X9241

DESCRIPTION

The X9241 integrates four nonvolatile E2POT digitally controlled potentiometers on a monolithic CMOS micro- circuit. The X9241 contains four resistor arrays, each com- posed of 63 resistive elements. Between each element and at either end are tap points accessible to the wiper elements. The position of the wiper element on the array is controlled by the user through the two-wire serial bus interface. Each resistor array has associated with it a wiper counter register and four 8-bit data registers that can be directly written and read by the user. The contents of the wiper counter register control the position of the wiper on the resistor array. The data register may be read or written by the user. The contents of the data registers can be transferred to the wiper counter register to position the wiper. The current wiper position can be transferred to any one of its associated data registers. The arrays may be cascaded to form resistive elements with 127, 190 or 253 taps. FUNCTIONAL DIAGRAM Terminal Voltage ±5V, 64 Taps A PPLICA TION NOTES AND DEVELOPMENT SYSTEM A V AILABLE AN20 • AN42–48 • AN50–53 • AN73 • XK9241 3864 ILL F07.1 R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VH1 VL1 VW1 R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 2 VH2 VL2 VW2 R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 3 VH3 VL3 VW3 INTERFACE AND CONTROL CIRCUITRY SCL SDA VH0 VL0 VW0 DATA

Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241. Potentiometer Pins VH (VH0 – VH3 ), VL (VL0 – VL3) The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiom- eter. V W (VW0 – VW3 ) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION PIN NAMES Symbol Description SCL Serial Clock SDA Serial Data A0–A3 Address VH0 –VH3, VL0–VL3 Potentiometers (terminal equivalent) VW0 –VW3 Potentiometers (wiper equivalent)

3864 PGM T01

The X9241 is a highly integrated microcircuit incorporat- ing four resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the E 2POT poten- tiometers. Serial Interface The X9241 supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. There- fore, the X9241 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (t LOW ). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9241 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (t HIGH ). The X9241 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA while SCL is HIGH. 3864 ILL F01A.2 VW0 VL0 VH0 VW1 VL1 VH1 SDA VSS VCC VW3 VL3 VH3 SCL VW2 VL2 VH2 DIP/SOIC/TSSOP X9241

X9241 will respond with a final acknowledge. the WCR can be read and written by the host system. Figure 1. Slave Address the X9241 to respond with an acknowledge. nal write cycle. ACK polling can be initiated immediately.

3864 ILL F01

100 A3 A2 A1 A0

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Figure 3. Two-Byte Command Sequence Figure 2. Instruction Byte Format Figure 3. These two-byte instructions exchange data

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0101 A 3 A 2 A 1 A 0 A

Figure 4. Three-Byte Command Sequence Figure 6. Increment/Decrement Timing Limits Figure 5. Increment/Decrement Command Sequence

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Figure 7. Acknowledge Response from Receiver Table 1. Instruction Set

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register organization and array operation follows. from the value present at power-down. operation and will take a maximum of 10ms. store system parameters or user preference data. Figure 8. Detailed Potentiometer Block Diagram

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order bits, CM (Cascade Mode) and DW (Disable Wiper). the potentiometer is in the normal operation mode. is cascaded with its adjacent higher order potentiometer. Figure 9. Cascading Arrays Increment/Decrement command. Register command must be issued before power-down.

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH – VL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. ABSOLUTE MAXIMUM RATINGS* Voltage on SCK, SCL or any Address Input with Respect to V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C

3864 PGM T03

X9241 5V ±10% 3864 PGM T04.1 ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions R TOTAL End to End Resistance –20 +20 % Power Rating 50 mW 25 °C, each pot IW Wiper Current –1 +1 mA R W Wiper Resistance 40 100 Ω Wiper Current = ± 1mA VTERM Voltage on any VH or –5 +5 V or VL Pin Noise ≤120 dB/ Ref: 1V Resolution (4) 1.6 0.4 % Absolute Linearity (1) –1 +1 MI (3) Vw(n)(actual) – Vw(n)(expected) Relative Linearity (2) –0.2 +0.2 MI (3) Vw(n + 1) – [Vw(n) + MI] Temperature Coefficient ±300 ppm/ °C 3864 PGM T05.2 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions lCC Supply Current (Active) 3 mA f SCL = 100KHz, SDA = Open, Other Inputs = VSS ISB VCC Current (Standby) 200 500 µA SCL=SDA=V CC , Addr. = VSS ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VIH Input HIGH Voltage 2 V CC + 1 V VIL Input LOW Voltage –1 0.8 V VOL Output LOW Voltage 0.4 V I OL = 3mA 3864 PGM T06.3

Guidelines for Calculating Typical Values of Bus Pull-Up Resistors CAPACITANCE Symbol Parameter Max. Units Test Conditions C I/O(5) Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN(5) Input Capacitance (A0, A1, A2, A3 and SCL) 6 pF V IN = 0V

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Symbol Parameter Max. Units tPUR (6) Power-up to Initiation of Read Operation 1 ms tPUW (6) Power-up to Initiation of Write Operation 5 ms

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A.C. CONDITIONS OF TEST Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels V CC x 0.5

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EQUIVALENT A.C. TEST CIRCUIT Notes: (5) This parameter is periodically sampled and not 100% tested. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 3864 ILL F02.1 1533Ω 100pF SDA OUTPUT

3864 ILL F17

RESISTANCE (K Ω ) BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE R MAX =C BUS tR R MIN = IOL MIN VCC MAX =1.8KΩ SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum Endurance 100,000 Data Changes per Register Data Retention 100 Years 3864 PGM T07.2

Figure 10. Input Bus Timing

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Figure 11. Output Bus Timing Figure 12. Start Stop Timing Figure 13. Write Cycle and Wiper Response Timing

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3864 ILL F05

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0.022 (0.559) 0.014 (0.356) (3.81) 0.150 (2.92) 0.1150 0.10 (BSC) (2.54) 1.060 (26.92) 0.980 (24.89) 0.900 (23.66) REF. PIN 1 INDEX 0.195 (4.95) 0.115 (2.92) 0.015 (0.38) 3926 FHD F18.1 PIN 1 SEATING PLANE 0.070 (1.778) 0.045 (1.143) 0.280 (7.11) 0.240 (6.096) 0.005 (0.127) 15° 20-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. P ACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.014 (0.356) 0.008 (0.2032) 0.300 (7.62) (BSC)

0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.496 (12.60) 0.508 (12.90) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 0.015 (0.40) 0.050 (1.27) 0.007 (0.18) 0.011 (0.28) 0° – 8° X 45°

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20-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

20 PlacesFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .252 (6.4) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

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ORDERING INFORMATION

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Device VCC Limits Blank = 5V ±10% Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 20-Lead Plastic DIP S = 20-Lead SOIC V = 20-Lead TSSOP Potentiometer Organization Pot 0 Pot 1 Pot 2 Pot 3 Y = 2K 2K 2K 2K W = 10K 10K 10K 10K U = 50K 50K 50K 50K M = 2K 10K 10K 50K X9241 Y P T V