X9241A_06 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
- Four potentiometers in one package
- 2-wire serial interface
- Register oriented format - Direct read/write/transfer of wiper positions - Store as many as four positions per potentiometer
- Terminal Voltages: +5V, -3.0V
- Cascade resistor arrays
- Low power CMOS
- High Reliability - Endurance–100,000 data changes per bit per register - Register data retention–100 years
- 16-bytes of nonvolatile memory
- 3 resistor array values -2 k Ω, 10kΩ, 50kΩ or combination - Cascadable for values of 4k Ω to 200kΩ
- Resolution: 64 taps each pot
- 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC packages
- Pb-free plus anneal available (RoHS compliant) Block Diagram Data R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 Wiper Counter Register (WCR) VH1/RH1 VL1/RL1 VW1/RW1 Register Array Pot 1 Wiper Counter Register (WCR) R1R0 R3R2 SCL SDA Interface and Control Circuitry VH2/ VL2/RL2 VW2/RW2 VH3/RH3 VL3/RL3 VW3/RW3 Register Array Pot 2 Wiper Counter Register (WCR) R1R0 R3R2 Register Array Pot 3 Wiper Counter Register (WCR) R1R0 R3R2 VCC VSS RH2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet FN8164.5 December 14, 2006
2 FN8164.5 December 14, 2006
Ordering Information
(V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) PACKAGE X9241AMP X9241AMP 5 ±10% 2/10/50 0 to +70 20 Ld PDIP X9241AMPZ (Note) X9241AMPZ 0 to +70 20 Ld PDIP* (Pb-free) X9241AMPI X9241AMPI -40 to +85 20 Ld PDIP X9241AMPIZ (Note) X9241AMPIZ -40 to +85 20 Ld PDIP* (Pb-free) X9241AMS* X9241AMS 0 to +70 20 Ld SOIC X9241AMSZ* (Note) X9241AMS Z 0 to +70 20 Ld SOIC (Pb-free) X9241AMSI* , ** X9241AMSI -40 to +85 20 Ld SOIC X9241AMSIZ* (Note) X9241AMSI Z -40 to +85 20 Ld SOIC (Pb-free) X9241AMV* X9241AMV 0 to +70 20 Ld TSSOP X9241AMVZ* (Note) X9241AMV Z 0 to +70 20 Ld TSSOP (Pb-free) X9241AMVI* , ** X9241AMVI -40 to +85 20 Ld TSSOP X9241AMVIZ* (Note) X9241AMVI Z -40 to +85 20 Ld TSSOP (Pb-free) X9241AWP X9241AWP 10 0 to +70 20 Ld PDIP X9241AWPI X9241AWPI -40 to +85 20 Ld PDIP X9241AWPIZ (Note) X9241AWPI Z -40 to +85 20 Ld PDIP*** (Pb-free) X9241AWS* , ** X9241AWS 0 to +70 20 Ld SOIC X9241AWSZ*, ** (Note) X9241AWS Z 0 to +70 20 Ld SOIC (Pb-free) X9241AWSI* X9241AWSI -40 to +85 20 Ld SOIC X9241AWSIZ* (Note) X9241AWSI Z -40 to +85 20 Ld SOIC (Pb-free) X9241AWV* , ** X9241AWV 0 to +70 20 Ld TSSOP X9241AWVZ* (Note) X9241AWVZ 0 to +70 20 Ld TSSOP (Pb-free) X9241AWVI* , ** X9241AWVI -40 to +85 20 Ld TSSOP X9241AWVIZ*, (Note) X9241AWVI Z -40 to +85 20 Ld TSSOP (Pb-free) X9241AYP X9241AYP 2 0 to +70 20 Ld PDIP X9241AYPZ (Note) X9241AYP Z 0 to +70 20 Ld PDIP* (Pb-free) X9241AYPI X9241AYPI -40 to +85 20 Ld PDIP X9241AYPIZ (Note) X9241AYPI Z -40 to +85 20 Ld PDIP*** (Pb-free) X9241AYS* X9241AYS 0 to +70 20 Ld SOIC X9241AYSZ* (Note) X9241AYS Z 0 to +70 20 Ld SOIC (Pb-free) X9241AYSI* X9241AYSI -40 to +85 20 Ld SOIC X9241AYSIZ* (Note) X9241AYSI Z -40 to +85 20 Ld SOIC (Pb-free) X9241AYV* , ** X9241AYV 0 to +70 20 Ld TSSOP X9241AYVZ* (Note) X9241AYV Z 0 to +70 20 Ld TSSOP (Pb-free) X9241AYVI* , ** X9241AYVI -40 to +85 20 Ld TSSOP X9241AYVIZ* (Note) X9241AYVI Z -40 to +85 20 Ld TSSOP (Pb-free) X9241A Pot 0 = 2k Pot 2 = 10k Pot 3 = 50k Pot 1 = 10k Pot 0 = 10k Pot 1 = 10k Pot 2 = 10k Pot 3 = 10k Pot 0 = 2k Pot 1 = 2k Pot 2 = 2k Pot 3 = 2k
3 FN8164.5 December 14, 2006 Pin Descriptions Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire- ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241A. Potentiometer Pins VH/RH(VH0/RH0—V H3/RH3), VL/RL (VL0/RL0—V L3/RL3) The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0—V W3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Pin Configuration X9241AUP X9241AUP 5 ±10% 50 0 to +70 20 Ld PDIP X9241AUPZ (Note) X9241AUP Z 0 to +70 20 Ld PDIP* (Pb-free) X9241AUPI X9241AUPI -40 to +85 20 Ld PDIP X9241AUPIZ (Note) X9241AUPI Z -40 to +85 20 Ld PDIP* (Pb-free) X9241AUS* , ** X9241AUS 0 to +70 20 Ld SOIC X9241AUSZ* (Note) X9241AUS Z 0 to +70 20 Ld SOIC (Pb-free) X9241AUSI*, ** X9241AUSI -40 to +85 20 Ld SOIC X9241AUSIZ* (Note) X9241AUSI Z -40 to +85 20 Ld SOIC (Pb-free) X9241AUV* X9241AUV 0 to +70 20 Ld TSSOP X9241AUVZ* (Note) X9241AUV Z 0 to +70 20 Ld TSSOP (Pb-free) X9241AUVI* , ** X9241AUVI -40 to +85 20 Ld TSSOP X9241AUVIZ* (Note) X9241AUVI Z -40 to +85 20 Ld TSSOP (Pb-free) *Add "T1" suffix for tape and reel. Add “T2” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Ordering Information (Continued) PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) PACKAGE Pin Names SYMBOL DESCRIPTION SCL Serial Clock SDA Serial Data A0–A3 Address VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0–VW3/RW3 Potentiometer Pins (wiper equivalent) VW0/RW0 VH1/RH1 SDA V SS V CC SCL DIP/SOIC/TSSOP X9241A VL0/RL0 VH0/RH0 VW1/RW1 VL1/RL1 VW3/RW3 VL3/RL3 VH3/RH3 VW2/RW2 VL2/RL2 VH2/RH2 X9241A Pot 0 = 50k Pot 1 = 50k Pot 2 = 50k Pot 3 = 50k
between the host and the XDCP potentiometers. The X9241A supports a bidirectional bus oriented protocol. bus as a transmitter and the receiving device as the receiver. considered a slave device in all applications. are reserved for indicating start and stop conditions. respond to any command until this condition is met. successfully received the eight bits of data. See Figure 7. respond with a final acknowledge. can be read and written by the host system. to Figure 1 below). For the X9241A this is fixed as 0101[B]. FIGURE 1. SLAVE ADDRESS
associated registers. The format is shown below in Figure 2. when a register oriented instruction is issued.
- These two-byte instructions exchange data between the
one of their associated registers. Four instructions require a three-byte sequence to complete. Register, write a new value to the selected Data Register. The sequence of operations is shown in Figure 4. steps; thereby, providing a fine tuning capability to the host. Figures 5 and 6 respectively. FIGURE 2. INSTRUCTION BYTE FORMAT
0101 A 3 A 2 A 1 A 0
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 1. INSTRUCTION SET FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
organization and array operation follows. contents of its Data Register zero (DR0) upon power-up. Each potentiometer has four nonvolatile Data Registers. will take a maximum of 10ms. system parameters or user preference data. FIGURE 8. DETAILED POTE NTIOMETER BLOCK DIAGRAM
10 FN8164.5 December 14, 2006 Notes: (1) Absolute Linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (R H–RL)/63, single pot (4) Max = all four arrays cascaded together, Typical = individual array resolutions. Absolute Maximum Ratings Recommended Operating Conditions Voltage on SCK, SCL or any address Voltage on any VH/RH, VW/RW or VL/RL Supply Voltage (VCC) Limits CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Specifications (Over recommended operating conditions unless otherwise stated.) SYMBOL PARAMETER TEST CONDITION LIMITS UNITMIN TYP MAX RTOTAL End to end resistance -20 +20 % RW Wiper resistance Wiper Current = ± 1mA 40 130 Ω VTERM Voltage on any VH/RH, VW/RW or VL/RL Pin -3.0 +5 V Noise Ref: 1kHz (Note 5) ≤120 dBV Resolution (Note 5) 1.6 % Absolute linearity (Note 1) R w(n)(actual) - Rw(n)(expected) ±1 MI (3) Relative linearity (Note 2) R w(n + 1) - [Rw(n) + MI]± 0 . 2 M I (3) Temperature coefficient of RTOTAL (Note 5) ±300 ppm/°C Ratiometric temperature coefficient (Note 5) ±20 ppm/C CH/CL/CW Potentiometer capacitances See Circuit #3 and (Note 5) 15/15/25 pF lAL RH, RI, RW leakage current V IN = VTERM. Device is in stand-by mode. 0.1 1 µA SYMBOL PARAMETER TEST CONDITION LIMITS UNITMIN TYP MAX lCC Supply current (active) f SCL = 100kHz, Write/Read to WCR, Other Inputs = VSS 3m A ISB VCC current (standby) SCL = SDA = V CC, Addr. = VSS 200 500 µA ILI Input leakage current V IN = VSS to VCC 10 µA ILO Output leakage current V OUT = VSS to VCC 10 µA VIH Input HIGH voltage 2 V VIL Input LOW voltage 0.8 V VOL Output LOW voltage I OL = 3mA 0.4 V X9241A
11 FN8164.5 December 14, 2006 Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. Notes: (5) This parameter is not 100% tested. (6) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. (7) This parameter is guaranteed by design. (8) Maximum Wiper Current is derated over tem perature. See the Wiper Current Derating Curve. (9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitc h pulse width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device. Symbol Table Equivalent AC Test Circuit Circuit #3 SPICE Macro Model Endurance and Data Retention PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Capacitance SYMBOL PARAMETER TEST CONDITION TYP UNIT CI/O (Note 5) Input/output capacitance (SDA) V I/O = 0V 19 pF CIN (Note 5) Input capacitance (A0, A1, A2, A3 and SCL) V IN = 0V 12 pF Power-up Timing SYMBOL PARAMETER MIN TYP MAX UNIT tPUR (Note 6) Power-up to initiation of read operation 1 ms tPUW (Note 6) Power-up to initiation of write operation 5 ms tRVCC VCC Power up ramp rate 0.2 50 V/ms AC Conditions of Test Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 1533Ω 100pF SDA Output RH CH 15pF CW RL CL RW RTOTAL 25pF 15pF Macro Model X9241A
FIGURE 10. INPUT BUS TIMING
14 FN8164.5 December 14, 2006 X9241A Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E
0.25 CABM
H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW
0.10 CABMb
c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE Rev. E 12/02 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.
15 FN8164.5 December 14, 2006 X9241A Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C
0.010 BM CA
B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8164.5 December 14, 2006 X9241A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N2 0 2 0 9 Rev. 0 12/93