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FN8163 Rev 2.00 Page 1 of 15 August 30, 2006 FN8163 Rev 2.00 August 30, 2006 X9221A

64 Taps, 2-Wire Serial Bus Dual Digitally Controlled Potentiometer (XDCP™)

FEATURES

  • Two XDCPs in one package
  • 2-wire serial interface
  • Register oriented format, 8 registers total —Directly write wiper position —Read wiper position —Store as many as four positions per pot
  • Instruction format —Quick transfer of register contents to resistor array
  • Direct write cell —Endurance–100,000 writes per bit per register
  • Resistor array values —2k, 10k, 50k
  • Resolution: 64 taps each pot
  • 20 Ld plastic DIP and 20 Ld SOIC packages
  • Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9221A integrates two digitally controlled potenti- ometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 2 non- volatile Data Registers (DR0:DR1) that can be directly written to and read by the user. The contents of the WCR controls the pos ition of the wiper on the resistor array through the switches. Power up recalls the con- tents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications in cluding control, parameter adjustments, and signal processing. BLOCK DIAGRAM R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 Wiper Counter Register (WCR) Register Array Pot 1 Wiper Counter Register (WCR) R1R0 R3R2 Data SCL SDA Interface and Control Circuitry VCC VSS Pot 0 VH1/RH1 VL1/RL1 VW1/RW1

FN8163 Rev 2.00 Page 2 of 15 August 30, 2006 PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to cloc k data into and out of the X9221A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open col- lector outputs. An open drai n output requires the use of a pull-up resistor. For select ing typical values, refer to the guidelines for calculatin g typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave add ress. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9221A Potentiometer Pins V H/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1) The VH/RH and VL/RL inputs are equivalent to the termi- nal connections on either end of a mechanical potenti- ometer. V W/RW (VW0/RW0-VW1/RW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION

Ordering Information

(V) RTOTAL (k) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9221AYS X9221AYS 5 ±10% 2 0 to +70 20 Ld SOIC (300MIL) MDP0027 X9221AYSZ (Note) X9221AYS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AYSI* X9221AYSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AYSIZ* (Note) X9221AYSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AWS* X9221AWS 10 0 to +70 20 Ld SOIC (300MIL) MDP0027 X9221AWSZ* (Note) X9221AWS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AWSI* X9221AWSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AWSIZ* (Note) X9221AWSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AUP X9221AUP 50 0 to +70 20 Ld PDIP MDP0031 X9221AUPZ (Note) X9221AUPZ 0 to +70 20 Ld PDIP (Pb-Free) MDP0031 X9221AUPI X9221AUPI -40 to +85 20 Ld PDIP MDP0031 X9221AUPIZ (Note) X9221AUPIZ -40 to +85 20 Ld PDIP (Pb-Free) MDP0031 X9221AUSI* X9221AUSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AUSIZ* (Note) X9221AUSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VW0/RW0 VL0/RL0 VH0/RL0 V W1/RW1 VL1/RL1 VH1/RH1 SDA VSS VCC RES RES RES SCL RES RES RES DIP/SOIC X9221A

X9221A will respond with a final acknowledge. select, and enable, one of sixty-four switches. the WCR can be read and written by the host system. Figure 1. Slave Address

Figure 3. Two-Byte Command Sequence Figure 4. Three-Byte Command Sequence Figure 5. Increment/Decrement Command Sequined

0101 A 3 A 2 A 1 A 0

Figure 6. Increment/Decrement Timing Limits Table 1. Instruction Set

Figure 7. Acknowledge Response from Receiver ister organization and array operation follows. its data register zero (R0) upon power-up. from the value present at power-down. Each potentiometer has four nonvolatile data registers. operation and will take a maximum of 10ms. store system parameters or user preference data.

Figure 8. Detailed Potentiometer Block Diagram

FN8163 Rev 2.00 Page 9 of 15 August 30, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, SCL or Any Address  Input With Respect to V Voltage on Any VH/RH, VW/RW or VL/RL  I COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit RTOTAL End to End Resistance -20 +20 % Power Rating 50 mW +25°C, each pot IW Wiper Current -3 +3 mA RW Wiper Resistance 40 130  Wiper Current = ±1mA VTERM Voltage on any VH/RH, VW/RW or  VL/RL Pin -3.0 +5 V Noise 120 dBV Ref: 1V Resolution 1.6 % See Note 5 Absolute Linearity(1) -1 +1 MI (3) Vw(n)(actual - Vw(n)(expected) Relative Linearity(2) -0.2 +0.2 MI (3) Vw(n + 1) - [Vw(n) + MI] Temperature Coefficient ±300 ppm/°C See Note 5 Radiometric Temperature Coefficient ±20 ppm/°C See Note 5 CH/CL/CW Potentiometer Capacitances 10/10/25 pF See circuit #3 RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 C+ 7 0 C Industrial -40 C+ 8 5 C Supply Voltage Limits X9221A 5V ± 10%

FN8163 Rev 2.00 Page 10 of 15 August 30, 2006 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute Linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (V H/RH–VL/RL)/63, single pot ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Notes: (5) This parameter is periodically sampled and not 100% tested. (6) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First V CC, then the potentiometer pi ns. It is suggested that V CC reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit lCC Supply Current (Active) 3 mA f SCL = 100kHz, SDA = Open, Other Inputs = VSS ISB VCC Current (Standby) 200 500 µA SCL = SDA = V CC, Addr. = VSS ILI Input Leakage Current 10 µA V IN = VSS to VCC ILO Output Leakage Current 10 µA V OUT = VSS to VCC VIH Input HIGH Voltage 2 V CC + 1 V VIL Input LOW Voltage -1 0.8 V VOL Output LOW Voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Parameter Max. Unit Test Conditions CI/O(5) Input/output capacitance (SDA) 8 pF V I/O = 0V CIN(5) Input capacitance (A0, A1, A2, A3 and SCL) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tPUR(6) Power-up to initiation of read operation 1 ms tPUW(6) Power-up to initiation of write operation 5 ms tRVCC VCC Power-up ramp rate 0.2 50 V/ms

FN8163 Rev 2.00 Page 11 of 15 August 30, 2006 A.C. CONDITIONS OF TEST SYMBOL TABLE Equivalent A.C. Test Circuit Circuit #3 SPICE Macro Model Guidelines for Calculating Typical Values of Bus Pull-Up Resistors Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 1533 100pF SDA Output RH CH 10pF CW RL CL RW RTOTAL 25pF 10pF Macro Model 120 100 20 40 60 80 100 120 Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX =CBUS tR RMIN = IOL MIN VCC MAX =1.8k Resistance (k)

FN8163 Rev 2.00 Page 12 of 15 August 30, 2006 A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated) Symbol Parameter Limits Unit Reference FigureMin. Max. fSCL SCL clock frequency 0 100 kHz 10 tLOW Clock LOW period 4700 ns 10 tHIGH Clock HIGH period 4000 ns 10 tR SCL and SDA rise time 1000 ns 10 tF SCL and SDA fall time 300 ns 10 Ti Noise suppression time constant (glitch filter) 100 ns 10 tSU:STA Start condition setup time (for a repeated start condition) 4700 ns 10 & 12 tHD:STA Start condition hold time 4000 ns 10 & 12 tSU:DAT Data in setup time 250 ns 10 tHD:DAT Data in hold time 0 ns 10 tAA SCL LOW to SDA data out valid 300 3500 ns 11 tDH Data out hold time 300 ns 11 tSU:STO Stop condition setup time 4700 ns 10 & 12 tBUF Bus free time prior to new transmission 4700 ns 10 tWR Write cycle time (nonvolatile write operation) 10 ms 13 tSTPWV Wiper response time from stop generation 1000 µs 13 tCLWV Wiper response from SCL LOW 500 µs 6

FN8163 Rev 2.00 Page 14 of 15 August 30, 2006 X9221A Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8163 Rev 2.00 Page 15 of 15 August 30, 2006 X9221A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. X9221A Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES N 8 14 16 18 20 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the l eads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c