X9221A INTERSIL | Alldatasheet

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Technical content

64 Taps, 2-Wire Serial Bus

Dual Digitally Controlled Potentiometer (XDCP™)

FEATURES

  • Two XDCPs in one package
  • 2-wire serial interface
  • Register oriented format, 8 registers total —Directly write wiper position —Read wiper position —Store as many as four positions per pot
  • Instruction format —Quick transfer of register contents to resistor array
  • Direct write cell —Endurance–100,000 writes per bit per register
  • Resistor array values —2k Ω, 10kΩ, 50kΩ
  • Resolution: 64 taps each pot
  • 20 Ld plastic DIP and 20-lead SOIC packages
  • Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9221A integrates two digitally controlled potenti- ometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 2 non- volatile Data Registers (DR0:DR1) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the con- tents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications in cluding control, parameter adjustments, and signal processing. BLOCK DIAGRAM R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 Wiper Counter Register (WCR) Register Array Pot 1 Wiper Counter Register (WCR) R1R0 R3R2 Data SCL SDA Interface and Control Circuitry VCC VSS Pot 0 VH1/RH1 VL1/RL1 VW1/RW1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet FN8163.1 September 14, 2005

2 FN8163.1 September 14, 2005

Ordering Information

PART NUMBER PART MARKING V CC LIMITS (V) R TOTAL (K) TEMP RANGE (°C) PACKAGE X9221AYP X9221AYP 5 ±10% 2 0 to 70 20 Ld PDIP X9221AYPZ (Note) X9221AYP Z 0 to 70 20 Ld PDIP (Pb-free) X9221AYPI X9221AYPI -40 to 85 20 Ld PDIP X9221AYPIZ (Note) X9221AYPI Z -40 to 85 20 Ld PDIP (Pb-Free) X9221AYS* X9221AYS 0 to 70 20 Ld SOIC (300MIL) X9221AYSZ* (Note) X9221AYS Z 0 to 70 20 Ld SOIC (300MIL) (Pb-Free) X9221AYSI* X9221AYSI -40 to 85 20 Ld SOIC (300MIL) X9221AYSIZ* (Note) X9221AYSI Z -40 to 85 20 Ld SOIC (300MIL) (Pb-Free) X9221AWP X9221AWP 10 0 to 70 20 Ld PDIP X9221AWPZ (Note) X9221AWP Z 0 to 70 20 Ld PDIP (Pb-Free) X9221AWPI X9221AWPI -40 to 85 20 Ld PDIP X9221AWPIZ (Note) X9221AWPI Z -40 to 85 20 Ld PDIP (Pb-Free) X9221AWS* X9221AWS 0 to 70 20 Ld SOIC (300MIL) X9221AWSZ* (Note) X9221AWS Z 0 to 70 20 Ld SOIC (300MIL) (Pb-Free) X9221AWSI* X9221AWSI -40 to 85 20 Ld SOIC (300MIL) X9221AWSIZ* (Note) X9221AWSI Z -40 to 85 20 Ld SOIC (300MIL) (Pb-Free) X9221AUP X9221AUP 50 0 to 70 20 Ld PDIP X9221AUPZ (Note) X9221AUP Z 0 to 70 20 Ld PDIP (Pb-Free) X9221AUPI X9221AUPI -40 to 85 20 Ld PDIP X9221AUPIZ (Note) X9221AUPI Z -40 to 85 20 Ld PDIP (Pb-Free) X9221AUS* X9221AUS 0 to 70 20 Ld SOIC (300MIL) X9221AUSZ* (Note) X9221AUS Z 0 to 70 20 Ld SOIC (300MIL) (Pb-Free) X9221AUSI* X9221AUSI -40 to 85 20 Ld SOIC (300MIL) X9221AUSIZ* (Note) X9221AUSI Z -40 to 85 20 Ld SOIC (300MIL) (Pb-Free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. X9221A

3 FN8163.1 September 14, 2005 PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9221A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical val- ues, refer to the guidelines for calculating typical val- ues on the bus pull-up resistors graph. Address The Address inputs are used to set the least signifi- cant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9221A Potentiometer Pins V H/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1) The VH/RH and VL/RL inputs are equivalent to the ter- minal connections on either end of a mechanical potentiometer. V W/RW (VW0/RW0-VW1/RW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION PIN NAMES PRINCIPLES OF OPERATION The X9221A is a highly integrated microcircuit incor- porating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9221A supports a bidirectional bus oriented pro- tocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initia te data transfers and pro- vide the clock for both transmit and receive operations. Therefore, the X9221A w ill be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (t LOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9221A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (t HIGH). The X9221A continu- ously monitors the SDA and SCL lines for the start condition, and will not resp ond to any command until this condition is met. Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA while SCL is HIGH. VW0/RW0 VL0/RL0 VH0/RL0 V W1/RW1 VL1/RL1 VH1/RH1 SDA VSS VCC RES RES RES SCL RES RES RES DIP/SOIC X9221A Symbol Description SCL Serial Clock SDA Serial Data A0–A3 Address V H0/RH0-VH1/RH1, VL0/RH0-VL1/RL0 Potentiometers (terminal equivalent) V W0/RW0-VW1/RW1 Potentiometers (wiper equivalent) RES Reserved (Do not connect) X9221A

the X9221A will respond with a final acknowledge. select, and enable, one of sixty-four switches. the WCR can be read and written by the host system. Figure 1. Slave Address for the X9221A to respond with an acknowledge. proceed with the next operation.

Figure 2. Instruction Byte Format ometers and one of their associated registers. sequence of operations is shown in Figure 4. shown in Figures 5 and 6 respectively. Figure 3. Two-Byte Command Sequence

0101 A 3 A 2 A 1 A 0 A I3 I2 I1 I0 0 P0 R1 R0

Table 1. Instruction Set Figure 7. Acknowledge Response from Receiver

register organization and array operation follows. tents of its data register zero (R0) upon power-up. ent from the value present at power-down. store system parameters or user preference data. Figure 8. Detailed Potentiometer Block Diagram

9 FN8163.1 September 14, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, SCL or Any Address Input With Respect to V Voltage on Any VH/RH, VW/RW or VL/RL I COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those indicated in the operational sections of this specifica- tion) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit RTOTAL End to End Resistance -20 +20 % Power Rating 50 mW 25°C, each pot IW Wiper Current -3 +3 mA RW Wiper Resistance 40 130 Ω Wiper Current = ±1mA VTERM Voltage on any VH/RH, VW/RW or VL/RL Pin -3.0 +5 V Noise ≤120 dBV Ref: 1V Resolution 1.6 % See Note 5 Absolute Linearity(1) -1 +1 MI (3) Vw(n)(actual - Vw(n)(expected) Relative Linearity(2) -0.2 +0.2 MI (3) Vw(n + 1) - [Vw(n) + MI] Temperature Coefficient ±300 ppm/°C See Note 5 Radiometric Temperature Coefficient ±20 ppm/°C See Note 5 CH/CL/CW Potentiometer Capacitances 10/10/25 pF See circuit #3 RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Supply Voltage Limits X9221A 5V ± 10% X9221A

10 FN8163.1 September 14, 2005 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute Linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (V H/RH–VL/RL)/63, single pot ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Notes: (5) This parameter is periodically sampled and not 100% tested. (6) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First V CC, then the potentiometer pi ns. It is suggested that V CC reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit lCC Supply Current (Active) 3 mA f SCL = 100kHz, SDA = Open, Other Inputs = VSS ISB VCC Current (Standby) 200 500 µA SCL = SDA = V CC, Addr. = VSS ILI Input Leakage Current 10 µA V IN = VSS to VCC ILO Output Leakage Current 10 µA V OUT = VSS to VCC VIH Input HIGH Voltage 2 V CC + 1 V VIL Input LOW Voltage -1 0.8 V VOL Output LOW Voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Parameter Max. Unit Test Conditions CI/O(5) Input/output capacitance (SDA) 8 pF V I/O = 0V CIN(5) Input capacitance (A0, A1, A2, A3 and SCL) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tPUR(6) Power-up to initiation of read operation 1 ms tPUW(6) Power-up to initiation of write operation 5 ms tRVCC VCC Power-up ramp rate 0.2 50 V/msec X9221A

11 FN8163.1 September 14, 2005 A.C. CONDITIONS OF TEST SYMBOL TABLE Equivalent A.C. Test Circuit Circuit #3 SPICE Macro Model Guidelines for Calculating Typical Values of Bus Pull-Up Resistors Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 1533Ω 100pF SDA Output RH CH 10pF CW RL CL RW RTOTAL 25pF 10pF Macro Model 120 100 20 40 60 80 100 120 Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX =CBUS tR RMIN = IOL MIN VCC MAX =1.8kΩ Resistance (kΩ) X9221A

14 FN8163.1 September 14, 2005 PACKAGING INFORMATION 0.022 (0.559) 0.014 (0.356) (3.81) 0.150 (2.92) 0.1150 0.10 (BSC) (2.54) 1.060 (26.92) 0.980 (24.89) 0.900 (23.66) Ref. Pin 1 Index 0.195 (4.95) 0.115 (2.92) 0.015 (0.38) Pin 1 Seating Plane 0.070 (1.778) 0.045 (1.143) 0.280 (7.11) 0.240 (6.096) 0.005 (0.127) 15° 20-Lead Plastic Dual In-Line Package Type P 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.014 (0.356) 0.008 (0.2032) 0.300 (7.62) (BSC) NOTE: X9221A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8163.1 September 14, 2005 PACKAGING INFORMATION 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.496 (12.60) 0.508 (12.90) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 20-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

20 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.007 (0.18) 0.011 (0.28) 0°–8° X 45° X9221A