X9119TV14IZ

X9119_08 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interfac e for Write, Read, and Transfer Operations of the Potentiometer
• Wiper Resistance, 40 Ω Typical @ VCC = 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up.
• Standby Current < 3µA Max CC: 2.7V to 5.5V Operation
• 1 0 0 kΩ End-to-End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9118
• Pb-Free available (RoHS compliant) Functional Diagram RH RL BUS RW INTERFACE CONTROL POT VCC VSS 2-WIRE BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kΩPOWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE AND Data Sheet July 9, 2008

2 FN8162.4 July 9, 2008 Detailed Functional Diagram

Ordering Information

(V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG.# X9119TV14I X9119 TVI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ (Note) X9119 TVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14 X9119 TV 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z (Note) X9119 TVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14Z-2.7* (Note) X9119 TVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9119TV14I-2.7 X9119 TVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ-2.7* (Note) X9119 TVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. SCL SDA WP INTERFACE AND CONTROL CIRCUITRY VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100KΩ CONTROL POWER ON RECALL X9119

3 FN8162.4 July 9, 2008

Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems Pinout X9119 (14 LD TSSOP) TOP VIEW Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9119. DEVICE ADDRESS (A 2–A0) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. VCC RL VSS 7 8 NC RWA2 RH NC SDA NCSCL WP Pin Assignments PIN NUMBER PIN NAME FUNCTION 1, 3, 10 NC No Connect

2 A0 Device Address for 2-wire bus

4 A2 Device Address for 2-wire bus

5 SCL Serial Clock for 2-wire bus

6 SDA Serial Data Input/Output for 2-wire bus

8W P Hardware Write Protect

9 A1 Device Address for 2-wire bus

11 R W Wiper terminal of the Potentiometer

12 R H High terminal of the Potentiometer

13 R L Low terminal of the Potentiometer

14 V CC System Supply Voltage

Intersil manufacturing and testing purposes. between the host and the digitally controlled potentiometer.

• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description Resistor Array Description The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system. Serial Interface Description SERIAL INTERFACE The X9119 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9119 will be considered a slave device in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 3). START CONDITION All commands to the X9119 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9119 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (Figure 3). SERIAL DATA PATH FROM INTERFACE REGISTER 0 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER RH RL RW 10 10 C O U N T E R D E C O D E IF WCR = 000[HEX] THEN RW = RL IF WCR = 3FF[HEX] THEN RW = RH WIPER (WCR) (DR0) CIRCUITRY REGISTER 1 (DR1) REGISTER 2 (DR2) REGISTER 3 (DR3)

FIGURE 1. DETAILED POTENTIOMETER BLO CK DIAGRAM SERIAL INTERFACE DESCRIPTION

successfully received the eight bits of data. respond with a final acknowledge (see Figure 2). FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

The A2–A0 bits in the ID byte is the internal slave address. device for read or write operations. TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT TABLE 3. INSTRUCTION SET NOTE: 1/0 = data is one or zero.

1. it may be written directly by the host via the write wiper
2. it may be written indirectly by transferring the contents of
3. it is loaded with the contents of its data register zero (R0)

contents are lost when the X9119 is powered-down. Registers. These can be read or written directly by the host. operation and will take a maximum of 10ms. TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)

• Read Wiper Counter Register – read the current wiper position of the selected potentiometer,
• Write Wiper Counter Register – change current wiper position of the selected potentiometer,
• Read Data Register – read the contents of the selected Data Register;
• Write Data Register – write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a data register is a write-to-nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers. Two instructions (Figure 4) require a two-byte sequence to complete. These instructions transfer data between the host and the X9119; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers the contents of the Wiper Counter Register to the specified Data Register. See “Instruction Format” on page 8 for more details. POWER-UP AND DOWN REQUIREMENTS There are no restrictions on the power-up condition of V CC and the voltages applied to the potentiometer pins provided that the V CC is always more positive than or equal to the voltages at RH, RL, and RW, i.e. VCC ≥ RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1ms after V CC reaches its final value. WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 VVVVVVVVVV (MSB) (LSB) Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NV NV NV NV NV NV NV NV NV NV MSB LSB X9119

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

00 X X0 0 X XX

0101 XX X

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (W RITE OR READ FOR WCR OR DATA REGISTERS)

0101 A 2 A 1 A 0

9 FN8162.4 July 9, 2008 WRITE DATA REGISTER (DR) TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR) TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR) NOTES: 1. A2 ~ A0”: stand for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 A2 A1 A0 R / W = 0 1100 R B R A 0 0 X X X X X X W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE0101A 2 1 A 0 R / W = 0 1110 R B R A 00 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P R / W = 1 1100 R B R A 00 X9119

10 FN8162.4 July 9, 2008 NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = R TOT/1023 or (RH – RL)/1023, single pot Absolute Maximum Ratings Voltage on SCL, SDA, or any address input Operating Conditions Supply Voltage (VCC) Limits (Note 4) Thermal Information http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications (Over recommended operation conditions unless otherwise stated.) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS End-to-End Resistance R TOTAL 100 k Ω End-to-End Resistance Tolerance ±20 % Power Rating +25°C, each pot 50 mW Wiper Current I W ±3 mA Wiper Resistance R W Wiper Current = ± 50µA, VCC = 5V 40 110 Ω Wiper Current = ± 50µA, VCC = 3V 150 300 Ω Voltage on any RH or RL Pin V TERM VSS = 0V V SS 5V Noise Ref: 1V -120 dBV Resolution 0.1 % Absolute Linearity (Note 1) R w(n)(actual) – Rw(n)(expected), where n = 8 to 1006 ±1 MI (Note 3) Rw(n)(actual) – Rw(n)(expected) (Note 4) ±1.5 ±2.0 MI (Note 3) Relative Linearity (Note 2) R w(m + 1) – [Rw(m) + MI], where m = 8 to 1006 ±0.5 MI (Note 3) Rw(m + 1) – [Rw(m) + MI] (Note 4) ±0.5 ±1.0 MI (Note 3) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient 20 ppm/°C Potentiometer Capacitancies C H/CL/CW See Macro model 10/10/25 pF X9119

11 FN8162.4 July 9, 2008 Capacitance NOTES: 6. Limits should be considered typi cal and are not production tested. 7. t PUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These parameters are not 100% tested. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Operating Specifications (Over the recommended operating conditions unless otherwise specified.) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNITS VCC supply current (active) ICC1 fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) 3m A VCC supply current (nonvolatile write) ICC2 fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) 5m A VCC current (standby) I SB VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, Standby State only) 3µ A Input leakage current I LI VIN = VSS to VCC 10 µA Output leakage current ILO VOUT = VSS to VCC 10 µA Input HIGH voltage V IH VCC x 0.7 V CC + 1 V Input LOW voltage V IL -1 V CC x 0.3 V Output LOW voltage V OL IOL = 3mA 0.4 V Output HIGH voltage V OH Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years TEST SYMBOL MAX UNITS TEST CONDITIONS Input/Output capacitance (SI) C IN/OUT (Note 6) 8 pF V OUT = 0V Input capacitance (SCL, WP, A1 and A0) C IN (Note 6) 6 pF V IN = 0V Power-Up Timing PARAMETER SYMBOL MIN MAX UNITS VCC Power-up Rate t r VCC (Note 6) 0.2 50 V/ms Power-up to Initiation of read operation t PUR (Note 7) 1 ms Power-up to Initiation of write operation t PUW (Note 7) 50 ms AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5 X9119

12 FN8162.4 July 9, 2008 Equivalent A.C. Load Circuit RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 1533Ω 100pF SDA OUTPUT 867Ω 100pF SDA OUTPUT AC Timing High-Voltage Write Cycle Timing PARAMETER SYMBOL MIN MAX UNITS Clock Frequency fSCL 400 kHz Clock Cycle Time tCYC 2500 ns Clock High Time tHIGH 600 ns Clock Low Time tLOW 1300 ns Start Setup Time tSU:STA 600 ns Start Hold Time tHD:STA 600 ns Stop Setup Time tSU:STO 600 ns SDA Data Input Setup Time t SU:DAT 100 ns SDA Data Input Hold Time t HD:DAT 0n s SCL and SDA Rise Time t R 300 ns SCL and SDA Fall Time t F 300 ns SCL Low to SDA Data Output Valid Time t AA 250 ns SDA Data Output Hold Time t DH 0n s Noise Suppression Time Constant at SCL and SDA Inputs T I 50 ns Bus Free Time (Prior to Any Transmission) t BUF 1300 ns A0, A1, A2 Setup Time t SU:WPA 0n s A0, A1, A2 Hold Time t HD:WPA 0n s High-Voltage Write Cycle Timing PARAMETER SYMBOL TYP MAX UNITS High-Voltage Write CycleTime (Store Instructions) t WR 51 0 m s XDCP Timing PARAMETER SYMBOL MIN MAX UNITS Wiper Response Time After theThird (Last) Power Supply is Stable t WRPO 51 0 µ s WiperResponse Time After Instruction Issued (All Load Instructions) tWRL 51 0 µ s X9119

13 FN8162.4 July 9, 2008 Symbol Table Timing Diagrams Start and Stop Timing Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance tSU:STA tHD:STA tSU:STO SCL SDA tR ( START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA X9119

14 FN8162.4 July 9, 2008 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing SCL SDA RW (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1, A2 TSU:WPA THD:WPA (START) (STOP) (ANY INSTRUCTION) X9119

15 FN8162.4 July 9, 2008 Applications information Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT C OMPARATOR WITH HYSTERESIS VS VO VO = (1+R2/R1)VS IADJ VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9119

16 FN8162.4 July 9, 2008 Application Circuits (Continued) ATTENUATOR FILTER INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO VO = G VS -1/2 £ G £ +1/2 GO = 1 + R2/R1 fc = 1/(2pRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB FREQUENCY µ R1, R2, C AMPLITUDE µ RA, RB C VO X9119

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8162.4 July 9, 2008 X9119 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06