X9119

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• 1024 resistor taps – 10-bit resolution
• 2-Wire serial interface for write, read, and transfer operations of the potentiometer
• Wiper resistance, 40 Ω typical at VCC = 5V
• Four nonvolatile data registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up.
• Standby current <3µA maximum CC: 2.7V to 5.5V operation
• 100k Ω end-to-end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per register
• 1 4 L d T S S O P
• L o w p o w e r C M O S
• Single supply version of the X9118
• Pb-free available (RoHS compliant)

FIGURE 1. FUNCTIONAL DIAGRAM

FN8162 Rev 5.00 Page 2 of 18 July 5, 2016

Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC refe rence voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wh eatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

Ordering Information

(Notes 2, 3)P A R T M A R K I N G VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE RoHS COMPLIANT PKG. DWG.# X9119TV14IZ X9119 TVZI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z X9119 TVZ 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ-2.7 (Note 1 ) X9119 TVZG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 NOTES: 1. Add “T1” suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9119 . For more information on MSL, please see tech brief TB363. FIGURE 2. DETAILED FUNCTIONAL DIAGRAM

FN8162 Rev 5.00 Page 3 of 18 July 5, 2016 Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open-drain output and may be wire-ORed with any number of open-drain or open collector outputs. An open-drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by a 2-wire master to supply a 2-wire serial clock to the X9119. DEVICE ADDRESS (A2–A0) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW, prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Principals of Operation The X9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides detail description of the following:

• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description Resistor Array Description The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 3 on page 4). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. Pin Configuration X9119 (14 LD TSSOP) TOP VIEW Pin Assignments PIN NUMBER PIN NAME FUNCTION 1, 3, 10 NC No connect

2 A0 Device address for 2-wire bus

4 A2 Device address for 2-wire bus

5 SCL Serial clock for 2-wire bus

6 SDA Serial data input/output for 2-wire bus

8W P Hardware write protect

9 A1 Device address for 2-wire bus

11 R W Wiper terminal of the potentiometer

12 R H High terminal of the potentiometer

13 R L Low terminal of the potentiometer

14 V CC System supply voltage

FN8162 Rev 5.00 Page 6 of 18 July 5, 2016 Instruction and Register

Description

Device Addressing: Identification Byte (ID and A) Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9119; this is fixed as 0101[B] (refer to Table 1). The A2–A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2–A0 input pins. The slave address is externally specified by the user. The X9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9119 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2–A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS. The R/W bit is the LSB and is be used to program the device for read or write operations. INSTRUCTION BYTE AND REGISTER SELECTION The next byte sent to the X9119 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (IOP[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2 Table 3 provides a complete summary of the instruction set opcodes. TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT TABLE 3. INSTRUCTION SET Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the wiper counter register. Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the wiper counter register. Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the data register pointed to RB-RA. RB-RA to the wiper counter register. the data register pointed to by RB-RA. NOTE: 1/0 = data is one or zero.

FN8162 Rev 5.00 Page 7 of 18 July 5, 2016 Instruction and Register WIPER COUNTER REGISTER (WCR) The X9119 contains a wiper counter register (refer to Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. It may be written directly by the host via the write wiper counter register instruction (serial load). 2. It may be written indirectly by transferring the contents of one of four associated data registers via the XFR data register. 3. It is loaded with the contents of its data register zero (R0) upon power-up. The wiper counter register is a volatile register; that is, its contents are lost when the X9119 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR0 TO DR3) The potentiometer has four 10-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the wiper counter register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0 ~1023). Four of the six instructions are four bytes in length. These instructions are:

• Read Wiper Counter Register – Reads the current wiper position of the selected potentiometer.
• Write Wiper Counter Register – Changes current wiper position of the selected potentiometer.
• Read Data Register – Reads the contents of the selected Data Register.
• Write Data Register – Writes a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 6 on page 8 . These 4-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write-to-nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers. Two instructions (Figure 7 on page 8) require a 2-byte sequence to complete. These instructions transfer data between the host and the X9119; either between the host and one of the data registers or directly between the host and the wiper counter register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified data register to the wiper counter register.
• XFR Wiper Counter Register to Data Register – This transfers the contents of the wiper counter register to the specified data register. See “ Instruction Format” on page 8 for more details. POWER-UP AND POWER-DOWN REQUIREMENTS There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the VCC is always more positive than or equal to the voltages at RH, RL, and RW, i.e., VCC ≥ RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1ms after VCC reaches its final value.

TABLE 4. WIPER CONTROL REGISTER, WCR (10- BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV)

FIGURE 6. TWO-BYTE INSTRUCTION SEQUENCE

00 X X 0 0 X X X

0101 XX X

FIGURE 7. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)

0101 A 2 A 1A 0

0101 A 2 A 1 A 0

FN8162 Rev 5.00 Page 9 of 18 July 5, 2016 TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR) TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR) S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0101A 2 1 A 0 R / W = 0 1110R B R A00 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P R / W = 1 1100R B R A00 NOTES: 4. A2 ~ A0”: stand for the device addresses sent by the master. 5. WCRx refers to wiper position data in the wiper counter register.

FN8162 Rev 5.00 Page 10 of 18 July 5, 2016 Absolute Maximum Ratings Voltage on SCL, SDA, or any address input Operating Conditions Supply Voltage (VCC) Limits (Note 9) Thermal Information CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. Analog Specifications (Over recommended operation conditions unless otherwise stated.) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 13)T Y P MAX (Note 13)U N I T End-to-End Resistance R TOTAL 100 k Ω End-to-End Resistance Tolerance ±20 % Power Rating +25°C, each pot 50 mW Wiper Current I W ±3 mA Wiper Resistance R W Wiper Current = ± 50µA, VCC = 5V 40 110 Ω Wiper Current = ± 50µA, VCC = 3V 150 300 Ω Voltage on any RH or RL Pin V TERM VSS = 0V V SS 5V Noise Ref: 1V -120 dBV Resolution 0.1 % Absolute Linearity (Note 6 )R w(n)(actual) – Rw(n)(expected), where n = 8 to 1006 ±1.5 MI (Note 8) Rw(n)(actual) – Rw(n)(expected) (Note 9)± 1 . 5 ± 2 . 0 M I (Note 8) Relative Linearity (Note 7)R w(m + 1) – [Rw(m) + MI], where m = 8 to 1006 ±0.5 MI (Note 8) Rw(m + 1) – [Rw(m) + MI] (Note 9) ±0.5 ±1.0 MI (Note 8) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temperature Coefficient 20 ppm/°C Potentiometer Capacitances C H/CL/CW See Macro model 10/10/25 pF NOTES: 6. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer. 7. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 8. MI = R TOT/1023 or (RH – RL)/1023, single potentiometer

FN8162 Rev 5.00 Page 11 of 18 July 5, 2016 Operating Specifications (Over the recommended operating conditions unless otherwise specified.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCC Supply Current (Active) I CC1 fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, active, read and volatile write states only) 3m A VCC Supply Current (Nonvolatile Write) ICC2 fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, active, non-volatile write state only) 5m A VCC Current (Standby) I SB VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, standby state only) 3µ A Input Leakage Current I LI VIN = VSS to VCC 10 µA Output Leakage Current I LO VOUT = VSS to VCC 10 µA Input HIGH Voltage V IH VCC x 0.7 V CC + 1 V Input LOW Voltage V IL -1 V CC x 0.3 V Output LOW Voltage V OL IOL = 3mA 0.4 V Output HIGH Voltage V OH Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance TEST SYMBOL TEST CONDITIONS MAX UNIT Input/Output Capacitance (SI) C IN/OUT (Note 11)V OUT = 0V 8 pF Input Capacitance (SCL, WP, A1 and A0) C IN (Note 11)V IN = 0V 6 pF Power-Up Timing PARAMETER SYMBOL MIN MAX UNIT VCC Power-Up Rate t r VCC (Note 11)0 . 2 5 0 V / m s Power-Up to Initiation Of Read Operation t PUR (Note 12)1 m s Power-Up to Initiation Of Write Operation t PUW (Note 12)5 0 m s NOTES: 11. Limits should be considered typical and are not production tested. 12. t PUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These parameters are not 100% tested. 13. Parameters with MIN and/or MA X limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5

FN8162 Rev 5.00 Page 12 of 18 July 5, 2016 Equivalent A.C. Load Circuit RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 1533Ω 100pF SDA OUTPUT 867Ω 100pF SDA OUTPUT AC Timing High-Voltage Write Cycle Timing PARAMETER SYMBOL MIN MAX UNIT Clock Frequency fSCL 400 kHz Clock Cycle Time tCYC 2500 ns Clock High Time tHIGH 600 ns Clock Low Time tLOW 1300 ns Start Set-Up Time tSU:STA 600 ns Start Hold Time tHD:STA 600 ns Stop Set-Up Time tSU:STO 600 ns SDA Data Input Set-Up Time t SU:DAT 100 ns SDA Data Input Hold Time t HD:DAT 0n s SCL and SDA Rise Time tR 300 ns SCL and SDA Fall Time tF 300 ns SCL Low to SDA Data Output Valid Time t AA 250 ns SDA Data Output Hold Time t DH 0n s Noise Suppression Time Constant at SCL and SDA Inputs T I 50 ns Bus Free Time (Prior to Any Transmission) t BUF 1300 ns A0, A1, A2 Set-Up Time t SU:WPA 0n s A0, A1, A2 Hold Time t HD:WPA 0n s High-Voltage Write Cycle Timing PARAMETER SYMBOL TYP MAX UNIT High-Voltage Write Cycle Time (Store Instructions) t WR 51 0 m s XDCP Timing PARAMETER SYMBOL MIN MAX UNIT Wiper Response Time After the Third (Last) Power Supply is Stable t WRPO 51 0 µ s Wiper Response Time After Instruction Issued (All Load Instructions) t WRL 51 0 µ s

FN8162 Rev 5.00 Page 17 of 18 July 5, 2016 X9119 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE July 5, 2016 FN8162.5 Updated entire datasheet applying Intersil’s new standards. Updated title. Updated Ordering Information table by removing obsolete parts, updating Note 1 and adding Note 3. Removed Lead temperature (soldering, 10s) from the Thermal Information section on page 10. Updated Absolute Linearity maximum specification from “±1” to “±1.5”. Added Revision History and About Intersil sections. Updated POD to the latest revision changes are as follows: Updated drawing to remove table and added land pattern.

FN8162 Rev 5.00 Page 18 of 18 July 5, 2016 Package Outline Drawing M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40

0.20 C B A

0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20

1.00 REF

0.65

1.20 MAX

0.25

0.05 MIN

0.15 MAX

(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW