X9118TV14IZ-2.7

X9118_09 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for Write, Read and Transfer Operations of the Potentiometer
• Wiper Resistance, 40 Ω Typical @ 5V
• Four Non-Volatile Data Registers for Each Potentiometer
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall: Loads Saved Wiper Position on Power-Up
• Standby Current < 15µA Max
• System V CC: 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 1 0 0 kΩ End to End Resistance
• Endurance: 100,000 Data Changes Per Bit Per Register
• 100 yr. Data Retention
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)

Ordering Information

(V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9118TV14 X9118 TV 5 ±10% 100 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z (Note 1) X9118 TVZ 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9118TV14I (Note 2) X9118 TVI -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ (Note 1) X9118 TVZI -40 to +85 14 Ld TSSOP (Pb-free) M14.173 X9118TV14-2.7 (Note 2) X9118 TVF 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z-2.7 (Note 1) X9118 TVZF 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9118TV14I-2.7 (Note 2) X9118 TVG -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ-2.7 (Note 1) X9118 TVZG -40 to +85 14 Ld TSSOP (Pb-free) M14.173 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 2. Not recommended for new designs. Data Sheet December 4, 2009

2 FN8161.4 December 4, 2009 Functional Diagram Detailed Functional Diagram Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems RH RL BUS RW INTERFACE CONTROL POT VCC VSS 2-WIRE BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kΩPOWER ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE AND SCL SDA WP INTERFACE AND CONTROL CIRCUITRY V+VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100KΩ CONTROL POWER ON RECALL X9118

3 FN8161.4 December 4, 2009 Pin Configuration X9118 (14 LD TSSOP) TOP VIEW Pin Descriptions Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9118. DEVICE ADDRESS (A1–A0) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system or digital supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Principles of Operation The X9118 is an integrated microcircuit incorporating a resistor array and its registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides a detailed description of the following:

• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description Resistor Array Description The X9118 is comprised of a resistor array. The array contains 1023, in effect, discrete resistive segments that are connected in series (see Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL inputs). Pin Assignments PIN (TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage

2 NC No Connect

3 A0 Device Address for 2-wire bus

4 SCL Serial Clock for 2-wire bus

6 SDA Serial Data Input/Output for 2-wire bus

8 V- Analog Supply Voltage

9 A1 Device Address for 2-wire bus

10 NC No Connect

W Wiper terminal of the Potentiometer

12 R H High terminal of the Potentiometer

13 R L Low terminal of the Potentiometer

14 V CC System Supply Voltage

enable, one of 1024 switches. the WCR can be read and written by the host system. The X9118 supports a bidirectional bus oriented protocol. bus as a transmitter and the receiving device as the receiver. considered a slave device in all applications. reserved for indicating start and stop conditions. See Figure 3. any command until this condition is met. See Figure 3. successfully received the eight bits of data. respond with a final acknowledge. See Figure 2. FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

the master can then proceed with the next operation. The A[1:0] bits in the ID byte are the internal slave address. FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT

01010 A 1 A 0 R / W

TABLE 3. INSTRUCTION SET to the Data Register pointed to by RB-RA.

1. 1/ ∅ = data is one or zero.

1. It may be written directly by the host via the write Wiper
2. It may be written indirectly by transferring the contents of
3. It is loaded with the contents of its Data Register zero

ensure proper loadings of the DR0 value into the WCR. Registers. These can be read or written directly by the host. operation and will take a maximum of 10ms.

• Read Wiper Counter Register – read the current wiper position of the potentiometer,
• Write Wiper Counter Register – change current wiper position of the potentiometer,
• Read Data Register – read the contents of the selected Data Register;
• Write Data Register – write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between the potentiometer and one of its associated registers. Two instructions (see Figure 4) require a two-byte sequence to complete. These instructions transfer data between the host and the X9118; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register.
• XFR Wiper Counter Register to Data Register –This transfers the contents of the specified Wiper Counter Register to the specified Data Register. See “Instruction Format” on page 8 for more details. Other POWER-UP AND DOWN REQUIREMENTS At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the voltage at V-. During power-up and power down, V CC, V+, and V- must reach their final values within 1ms of each other.

TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)

9 FN8161.4 December 4, 2009 Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) NOTES: 1. “A1 ~ A0”: stands for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register. S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K Wiper Position or Data (Sent by Master on SDA) S A C K Wiper Position or Data (Sent by Master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01010A 1A 0 R/W = 0 1100R BR A00 XX XXXX W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01010A 1 A 0 R/W = 0 1110 R B R A 00 S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K S T O P01010A 1A 0 R/W = 1 1100R B R A00 X9118

10 FN8161.4 December 4, 2009 Absolute Maximum Ratings Thermal Information Voltage on SCL, SDA, or Any Address Input Any Voltage on R Supply Voltage (VCC) Limits (Note 7) Thermal Resistance (Typical, Note 3) θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications Over the recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RTOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % RW Wiper Resistance I W = (VRH - VRL)/RTOTAL, VCC = 3V, VRL = -3V 150 500 Ω RW Wiper Resistance I W = (VRH - VRL)/RTOTAL, VCC = 5V, VRL = 0V 40 100 Ω Vv+ Voltage on V+ Pin X9118 (Note 7) +4.5 +5.5 V Vv- Voltage on V- Pin X9118 -5.5 -4.5 V VTERM Voltage on any RH or RL Pin V SS = 0V V- V+ V Noise Ref: 1kHz -120 dBV Resolution 0.1 % Absolute Linearity (Note 4) R w(n)(actual) – Rw(n)(expected), where n = 1 to 1023 ±1.5 MI (Note 6) Relative Linearity (Note 5) R w(m + 1) – [Rw(m) + MI], where m = 1 to 1023 ±1.5 MI (Note 6) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temperature Coefficient Wiper at middle point ±20 ppm/°C CH/CL/CW Potentiometer Capacitances See Macro model 10/10/25 pF NOTES: 4. Absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 6. MI = R TOT/1023 or (RH – RL)/1023, single pot 7. V CC, V+, V- must reach their final values within 1ms of each other. X9118

11 FN8161.4 December 4, 2009 DC Operating SpecificationsOver the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC Supply Current (Active) f SCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) 3m A ICC2 VCC Supply Current (Nonvolatile Write) f SCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) 7m A ISB VCC Current (Standby) V CC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, Standby State only) 15 μA ILI Input Leakage Current V IN = VSS to VCC 10 μA ILO Output Leakage Current V OUT = VSS to VCC 10 μA VIH Input HIGH Voltage VCC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TYP UNITS TEST CONDITIONS CIN/OUT (Note 9) Input/Output Capacitance (SI) 8 pF V OUT = 0V CIN (Note 9) Input Capacitance (SCL, WP , A1 and A0) 6 pF V IN = 0V Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 9) VCC Power-up Rate 0.2 50 V/ms tPUR (Note 10) Power-up to Initiation of Read Operation 1 ms tPUW (Note 10) Power-up to Initiation of Write Operation 50 ms NOTES: 9. This parameter is not 100% tested 10. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5 X9118

12 FN8161.4 December 4, 2009 Equivalent A.C. Load Circuit RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 1533Ω 100pF SDA OUTPUT 867Ω 100pF SDA OUTPUT AC Timing High-Voltage Write Cycle Timing SYMBOL PARAMETER MIN MAX UNITS fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 250 ns tDH SDA Data Output Hold Time 0 ns tI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1300 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0n s High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-Voltage Write Cycle Time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER TYP UNITS tWRPO Wiper Response Time After the Third (last) Power Supply is Stable 8 µs tWRL Wiper Response Time After Instruction Issued (all load instructions) 8 µs X9118

13 FN8161.4 December 4, 2009 Symbol Table Timing Diagrams Start and Stop Timing Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA X9118

14 FN8161.4 December 4, 2009 XDCP Timing (For All Load Instructions) Write Protect and Device Address Pins Timing Applications Information Basic Configurations of Electronic Potentiometers SCL SDA RW (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (Any Instruction) VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current X9118

15 FN8161.4 December 4, 2009 Application Circuits NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10κΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9118

16 FN8161.4 December 4, 2009 Application Circuits (Continued) ATTENUATOR FILTER INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9118

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8161.4 December 4, 2009 X9118 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06