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Technical content

Features

  • 1024 resistor taps – 10-bit resolution
  • 2-wire serial interface for write, read and transfer operations of the potentiometer
  • Wiper resistance, 40 typical @ 5V
  • Four non-volatile data registers for each potentiometer
  • Non-volatile storage of multiple wiper positions
  • Power on recall: Loads saved wiper position on power-up
  • Standby current < 15µA Max
  • System V CC: 2.7V to 5.5V operation
  • Analog V+/V-: -5V to +5V
  • 1 0 0 k end-to-end resistance
  • Endurance: 100,000 data changes per bit per register
  • 100 years data retention
  • 14 Ld TSSOP
  • Low power CMOS
  • Pb-free (RoHS compliant)

Ordering Information

(Notes 1, 2) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # X9118TV14IZ X9118 TVZI 5 ±10% 100 -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ-2.7 X9118 TVZG 2.7 to 5.5 100 -40 to +85 14 Ld TSSOP M14. 173 X9118TV14Z X9118 TVZ 5 ±10% 100 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z-2.7 X9118 TVZF 2.7 to 5.5 100 0 to +70 14 Ld TSSOP M14.173 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 2. For Moisture Sensitivity Level (MSL), please see product information page for X9118 . For more information on MSL, please see tech brief TB363.

FN8161 Rev 5.00 Page 2 of 17 April 9, 2014 Functional Diagram Detailed Functional Diagram Circuit Level Applications

  • Vary the gain of a voltage amplifier
  • Provide programmable DC reference voltages for comparators and detectors
  • Control the volume in audio circuits
  • Trim out the offset voltage error in a voltage amplifier circuit
  • Set the output voltage of a voltage regulator
  • Trim the resistance in Wheatstone bridge circuits
  • Control the gain, characteristic frequency and Q-factor in filter circuits
  • Set the scale factor and zero point in sensor signal conditioning circuits
  • Vary the frequency and duty cycle of timer ICs
  • Vary the DC biasing of a pin diode attenuator in RF circuits
  • Provide a control variable (I, V, or R) in feedback circuits System Level Applications
  • Adjust the contrast in LCD displays
  • Control the power level of LED transmitters in communication systems
  • Set and regulate the DC biasing point in an RF power amplifier in wireless systems
  • Control the gain in audio and home entertainment systems
  • Provide the variable DC bias for tuners in RF wireless systems
  • Set the operating points in temperature control systems
  • Control the operating point for sensors in industrial systems
  • Trim offset and gain errors in artificial intelligent systems RH RL BUS RW INTERFACE CONTROL POT VCC VSS 2-WIRE BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kPOWER ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE AND SCL SDA WP INTERFACE AND CONTROL CIRCUITRY V+VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100K CONTROL POWER ON RECALL

FN8161 Rev 5.00 Page 3 of 17 April 9, 2014 Pinout X9118 (14 LD TSSOP) TOP VIEW Pin Descriptions Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bi-directional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. The user must account for the capacitance on the bus line and the desired rise and fall times when selecting a pull-up resistor. 2kΩ to 2.5kΩ are typical values when using the maximum clock frequency. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9118. DEVICE ADDRESS (A1–A0) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input, in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system or digital supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Principles of Operation The X9118 is an integrated microcircuit incorporating a resistor array and its registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides a detailed description of the following:

  • Resistor Array Description
  • Serial Interface Description
  • Instruction and Register Description Pin Assignments PIN # PIN NAME FUNCTION

1 V+ Analog Supply Voltage

2, 10 NC No Connect

3 A0 Device Address for 2-wire bus

4 SCL Serial Clock for 2-wire bus

5W P Hardware Write Protect

6 SDA Serial Data Input/Output for 2-wire bus

8 V- Analog Supply Voltage

9 A1 Device Address for 2-wire bus

W Wiper terminal of the Potentiometer

12 R H High terminal of the Potentiometer

13 R L Low terminal of the Potentiometer

14 V CC System Supply Voltage

WCR can be read and written by the host system. command until this condition is met, see Figure 3. FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

master can then proceed with the next operation. 0101[B] (refer to Table 1 on page 6). The A[1:0] bits in the ID byte are the internal slave address. FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER

TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT

01010 A 1 A 0 R / W

TABLE 3. INSTRUCTION SET to the Data Register pointed to by RB-RA.

  1. 1/ = data is one or zero.
  1. It may be written directly by the host via the write Wiper

Counter Register instruction (serial load).

  1. It may be written indirectly by transferring the contents of
  2. It is loaded with the contents of its Data Register zero (R0)

loadings of the DR0 value into the WCR. The potentiometer has four 10-bit non-volatile Data Registers.

  • Read Wiper Counter Register – Read the current wiper position of the potentiometer.
  • Write Wiper Counter Register – Change current wiper position of the potentiometer.
  • Read Data Register – Read the contents of the selected Data Register.
  • Write Data Register – Write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in

Figure 3. These four-byte instructions exchange data between nonvolatile memory and takes a minimum of tWR to complete.

  • XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register.
  • XFR Wiper Counter Register to Data Register –This transfers the contents of the specified Wiper Counter Register to the specified Data Register. Refer to “Instruction Format” on page 8 for more details. Other POWER-UP AND POWER-DOWN REQUIREMENTS At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the volt age at V-. During power-up and power-down, V CC, V+, and V- must rea ch their final values within 1ms of each other.

TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9 TO WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9 TO BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)

FN8161 Rev 5.00 Page 9 of 17 April 9, 2014 Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) NOTES: 1. “A1 ~ A0”: stands for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register. S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01 01 0 A 1 A 0 R/W = 0 1 1 0 0 R BR A00 X XXXXX W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01010A 1 A 0 R/W = 0 111 0R B R A 00 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P01010A 1A 0 R/W = 1 1 1 0 0 RB RA 0 0

FN8161 Rev 5.00 Page 10 of 17 April 9, 2014 Absolute Maximum Ratings Thermal Information Voltage on SCL, SDA, or Any Address Input Supply Voltage (VCC) Limits (Note 8) Thermal Resistance (Typical, Note 3, 4) . JA (°C/W) JC (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is taken at the package top center. Analog Specifications TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range , -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS RTOTAL End to End Resistance 100 k  End to End Resistance Tolerance ±20 % RW Wiper Resistance I W = (VRH - VRL)/RTOTAL, VCC = 3V, VRL = -3V 150 500  RW Wiper Resistance I W = (VRH - VRL)/RTOTAL, VCC = 5V, VRL = 0V 40 100  Vv+ Voltage on V+ Pin X9118 (Note 8) +4.5 +5.5 V Vv- Voltage on V- Pin X9118 -5.5 -4.5 V VTERM Voltage on any RH or RL Pin V SS = 0V V- V+ V Noise Ref: 1kHz -120 dBV Resolution 0.1 % Absolute Linearity (Note 5) R w(n)(actual) – Rw(n)(expected), where n = 1 to 1023 ±1.5 MI (Note 7) Relative Linearity (Note 6) R w(m + 1) – [Rw(m) + MI], where m = 1 to 1023 ±1.5 MI (Note 7) Temperature Coefficient of RTOTAL 300 ppm/°C Ratiometric Temperature Coefficient Wiper at middle point 20 ppm/°C CH/CL/CW Potentiometer Capacitances See Macro model 10/10 /25 pF NOTES: 5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 7. MI = RTOT/1023 or (RH – RL)/1023, single pot. 8. VCC, V+, V- must reach their final values within 1ms of each other.

FN8161 Rev 5.00 Page 11 of 17 April 9, 2014 DC Operating Specifications TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range , -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS ICC1 VCC Supply Current (Active) f SCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) 3 mA ICC2 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) 7 mA ISB VCC Current (Standby) V CC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, Standby State only) 15 A ILI Input Leakage Current V IN = VSS to VCC 10 A ILO Output Leakage Current V OUT = VSS to VCC 10 A VIH Input HIGH Voltage VCC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V NOTE: 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TYP UNITS TEST CONDITIONS CIN/OUT (Note 11) Input/Output Capacitance (SI) 8 pF V OUT = 0V CIN (Note 11) Input Capacitance (SCL, WP , A1 and A0) 6 pF V IN = 0V Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 11) VCC Power-up Rate 0.2 50 V/ms tPUR (Note 12) Power-up to Initiation of Read Operation 1 ms tPUW (Note 12) Power-up to Initiation of Write Operation 50 ms NOTES: 11. This parameter is not 100% tested. 12. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5

FN8161 Rev 5.00 Page 12 of 17 April 9, 2014 Equivalent A.C. Load Circuit RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 1533Ω 100pF SDA OUTPUT 867Ω 100pF SDA OUTPUT AC Timing High-Voltage Write Cycle Timing SYMBOL PARAMETER MIN MAX UNITS fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High-Time 600 ns tLOW Clock Low-Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 250 ns tDH SDA Data Output Hold Time 0 ns tI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1300 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0n s High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-Voltage Write Cycle Time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER TYP UNITS tWRPO Wiper Response Time After the Third (last) Power Supply is Stable 8 µs tWRL Wiper Response Time After Instruction Issued (all load instructions) 8 µs

FN8161 Rev 5.00 Page 13 of 17 April 9, 2014 Symbol Table Timing Diagrams Start and Stop Timing Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA

FN8161 Rev 5.00 Page 14 of 17 April 9, 2014 XDCP Timing (For All Load Instructions) Write Protect and Device Address Pins Timing Applications Information Basic Configurations of Electronic Potentiometers SCL SDA RW (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (ANY INSTRUCTION) VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current

FN8161 Rev 5.00 Page 15 of 17 April 9, 2014 X9118 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Application Circuits NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1

FN8161 Rev 5.00 Page 16 of 17 April 9, 2014 Application Circuits (Continued) ATTENUATOR FILTER INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO VO = G VS -1/2  G  +1/2 GO = 1 + R2/R1 fc = 1/(2RC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR R4 R1 = R2 = R3 = R4 = 10kW VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency  R1, R2, C amplitude  RA, RB C VO

FN8161 Rev 5.00 Page 17 of 17 April 9, 2014 Package Outline Drawing M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40

0.20 C B A

0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20

1.00 REF

0.65

1.20 MAX

0.25

0.05 MIN

0.15 MAX

(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW