X9118

X9118 INTERSIL | Alldatasheet

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FN8161.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PRELIMINARY X9118 Dual Supply/Low Power/1024-Tap/2-Wire Bus Single Digitally-Controlled (XDCP™) Potentiometer

DESCRIPTION

The X9118 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

FEATURES

• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface fo r write, read, and transfer operations of the potentiometer
• Wiper Resistance, 40 Ω Typical @ 5V
• Four Non-Volatile Data Registers for Each Potentiometer
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 3µA Max
• System V CC: - 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 1 0 0 kΩ End to End Resistance
• Endurance: 100, 000 Data changes per bit per register
• 100 yr. Data Retention
• 14-Lead TSSOP
• Low power CMOS FUNCTIONAL DIAGRAM R H R L Bus RW Interface & Control POT VCC VSS 2-Wire Bus Address Data Status Write Read Wiper 1024-tapsTransfer NC NC 100kΩPower On Recall Wiper Counter Register (WCR) Data Registers (DR0-DR3)Control Interface Data Sheet March 25, 2005

2 FN8161.1 March 25, 2005 DETAILED FUNCTIONAL DIAGRAM CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems SCL SDA WP Interface and Control Circuitry V+VCC VSS DR0 DR1 DR2 DR3 Wiper Counter Register (WCR) R H R L Data RW 1024-taps 100kΩ Control Power On Recall X9118

3 FN8161.1 March 25, 2005 PIN CONFIGURATION PIN DESCRIPTIONS Bus Interface Pins S ERIAL DATA INPUT /OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. S ERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9118. D EVICE ADDRESS (A1–A0) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus. H ARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins R H , RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. R W The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC ) AND SUPPLY G ROUND (VSS ) The VCC pin is the system or digital supply voltage. The VSS pin is the system ground. A NALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins N O CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. PIN ASSIGNMENTS PIN (TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage

2 NC No Connect

3 A0 Device Address for 2-wire bus

4 SCL Serial Clock for 2-wire bus

6 SDA Serial Data Input/Output for 2-wire

8V - Analog Supply Voltage

9 A1 Device Address for 2-wire bus

10 NC No Connect

11 R W Wiper terminal of the Potentiometer

12 R H High terminal of the Potentiometer

13 R L Low terminal of the Potentiometer

14 V CC System Supply Voltage

Figure 1. Detailed Potentiometer Block Diagram slave device in all applications.

while SCL is HIGH. See Figure 3. byte the X9118 will respond with a final acknowledge. Figure 2. Acknowledge Response from Receiver then proceed with the next operation.

X9118; this is fixed as 0101[B] (refer to Table 1). the device for read or write operations. four registers. The format is shown below in Table 2. Table 1. Identification Byte Format Table 2. Instruction Byte Format

Table 3. Instruction Set different from the value present at power-down. proper loadings of the DR0 value into the WCR . parameters or user preference data. Note: (1) 1/o = data is one or zero.

Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V) Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV) Four of the six instructions are four bytes in length. between the host and the Wiper Counter Register. Register to the Wiper Counter Register. Counter Register to the specified Data Register. See Instruction format for more details. Figure 3. Two-Byte Instruction Sequence

Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)

10 FN8161.1 March 25, 2005 Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Notes: (1) “A1 ~ A0”: stand for the device addresses sent by the master. (2) WCRx refers to wiper position data in the Wiper Counter Register S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K Wiper Position or Data (Sent by Master on SDA)S A C K Wiper Position or Data (Sent by Master on SDA)S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01010A 1A 0 R / W = 0 1100R BR A00 XX XXXX W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 01010A 1 A 0 R / W = 0 1110 R B R A 00 S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode Register Addresses S A C K S T O P01010A 1A 0 R / W = 1 1100R B R A00 X9118

11 FN8161.1 March 25, 2005 ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units R TOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % Power Rating 50 mW 25°C, each pot IW Wiper Current ±3 mA R W Wiper Resistance 150 500 Ω Wiper Current = ± 3mA, VCC = 3V R W Wiper Resistance 40 100 Ω IW = ± 3mA, VCC = 5V Vv+ Voltage on V+ pin +4.5 +5.5 V X9118 (4) Vv- Voltage on V- pin -5.5 -4.5 V X9118 VTERM Voltage on any RH or RL Pin V- V+ V V SS = 0V Noise -120 dBV Ref: 1V Resolution 0.1 % Absolute Linearity (1) ±1 MI (3) R w(n)(actual) – Rw(n)(expected), where n=8 to 1006 ±1.5 MI (3) R w(n)(actual) – Rw(n)(expected)(5) Relative Linearity(2) ±0.5 MI (3) R w(m + 1) – [Rw(m) + MI], where m=8 to 1006 ±1 MI (3) R w(m + 1) – Rw(m) + MI Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient 20 ppm/°C C H /CL/CW Potentiometer Capacitancies 10/10/25 pF See Macro model ABSOLUTE MAXIMUM RATINGS Voltage on SCL, SDA, or any address input with respect to V Any Voltage on R COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (V CC ) Limits(4) X9118 5V ±10% X9118-2.7 2.7V to 5.5V X9118

12 FN8161.1 March 25, 2005 Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot (4) VCC , V+, V- must reach their final values within 1 msec of each other. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 3m A f SCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) ICC2 VCC supply current (nonvolatile write) 5m A f SCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) ISB VCC current (standby) 3 µAV CC = +5.5V; VIN = VSS or VCC ; SDA = VCC ; (for 2-wire, Standby State only) ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage -1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage Parameter Min. Units Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Symbol Test Max. Units Test Conditions C IN/OUT(6) Input/Output capacitance (SI) 8 pF V OUT = 0V C IN(6) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC Power-up Rate 0.2 50 V/ms tPUR (7) Power-up to Initiation of read operation 1 ms tPUW (7) Power-up to Initiation of write operation 50 ms X9118

13 FN8161.1 March 25, 2005 A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT AC TIMINGHIGH-VOLTAGE WRITE CYCLE TIMING Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 R H 10pF C L C L R W R TOTAL C W 25pF 10pF R L SPICE Macromodel 1533Ω 100pF SDA OUTPUT 867Ω 100pF SDA OUTPUT Symbol Parameter Min. Max. Units fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 0 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 250 ns tDH SDA Data Output Hold Time 0 ns TI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1300 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns X9118

14 FN8161.1 March 25, 2005 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE TIMING DIAGRAMS Start and Stop Timing Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 51 0 µ s WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF X9118

15 FN8161.1 March 25, 2005 Input Timing Output Timing XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA SCL SDA RW (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (Any Instruction) X9118

16 FN8161.1 March 25, 2005 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +V R I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO R 2 R 1 VO = (1+R2/R1)VS R 1 R 2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R 2R 1 VUL = {R1/(R1+R 2)} VO (max) RL L = {R1/(R1+R 2)} VO (min) 100kΩ 10κΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R 2R 1 X9118

17 FN8161.1 March 25, 2005 Application Circuits (Continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO R 3 R 1 VO = G VS -1/2 ≤ G ≤ +1/2 G O = 1 + R2/R1 fc = 1/(2πRC) VS VO R 2R 1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq 1 + R3) >> R2 VS Function Generator R 2 R 4 R 1 = R2 = R3 = R4 = 10kΩ VS R 2 R 1 R C VO = G VS G = - R2/R1 R 2C 1 R 1 R 3 ZIN – R 2 R 1 R A R B frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9118

18 FN8161.1 March 25, 2005 a b Top View (Bump Side Down) Side View (Bump Side Down) Bottom View (Bump Side Up) c d e f k a j b Note: Drawing not to scale = Die Orientation mark l m XX-ball BGA (X9118xxxxxxx) Symbol Millimeters Inches M i nN o m .M a x M i nN o m .M a x Package Body Dimension X a Package Body Dimension Y b Package Height c Package Body Thickness d Ball Height e Ball Diameter f Total Ball Count g Ball Count X Axis h Ball Count Y Axis i Pins Pitch XAxis j Pins Pitch Y Axis k Edge to Ball Center (Corner) Distance Along X l Edge to Ball Center (Corner) Distance Along Y m X9118

19 FN8161.1 March 25, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X9118

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8161.1 March 25, 2005

ORDERING INFORMATION

Blank = 5V ±10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package V14 = 14-Lead TSSOP Potentiometer Organization Pot T = 100k Ω X9118