X9111TV14Z

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Document overview

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• PDF pages: 19

Technical content

Features

• 1024 resistor taps – 10-bit resolution
• SPI serial interface for write, read, and transfer operations of the potentiometer
• Wiper resistance, 40 Ω typical at 5V
• Four nonvolatile Data Registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up
• Standby current <3µA maximum CC: 2.7V to 5.5V operation
• 100k Ω end-to-end resistance
• 100-year data retention
• Endurance: 100,000 data changes per bit per register
• 1 4 L d T S S O P
• Low-power CMOS
• Single supply version of the X9110
• Pb-Free (RoHS compliant)

FIGURE 1. FUNCTIONAL DIAGRAM

FN8159 Rev 5.00 Page 2 of 19 October 13, 2016 Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC refe rence voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wh eatstone bridge circuits
• Control the gain, characteristic frequency, and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

Ordering Information

(Notes 2, 3) PART MARKING V CC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE (RoHS COMPLIANT) PKG. DWG. # X9111TV14IZ X9111TV ZI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9111TV14Z X9111TV Z 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9111TV14IZ-2.7 (Note 1 ) X9111TV ZG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 NOTES: 1. Add “T1” suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see product information page for X9111 . For more information on MSL, see tech brief TB363. Detailed Functional Diagram FIGURE 2. DETAILED FUNCTIONAL DIAGRAM

FN8159 Rev 5.00 Page 3 of 19 October 13, 2016 Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9111. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0, A1) The address inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input (A1–A0) in order to initiate communication with the X9111. CHIP SELECT (CS) When CS is HIGH, the X9111 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9111, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT (NC) Pin should be left open. This pin is used for Intersil manufacturing and test purposes. Pin Configuration X9111 (14 LD TSSOP) TOP VIEW Pin Descriptions PIN (TSSOP) SYMBOL FUNCTION

1 SO Serial Data Output

2 A0 Device Address

3 NC No Connect

5 SCK Serial Clock

6S I S e r i a l D a t a I n p u t SS System Ground 8W P Hardware Write Protect

9 A1 Device Address

10 HOLD Device Select. Pause the Serial Bus

11 R W Wiper Terminal of the Potentiometer

12 R H High Terminal of the Potentiometer

13 R L Low Terminal of the Potentiometer

14 V CC System Supply Voltage

during the entire operation. state outputs. This can help to reduce system pin count. individual array, only one switch may be turned on at a time. and enable, one of 1024 switches.

1. It may be written directly by the host via the write Wiper

Counter Register instruction (serial load).

1. It may be written indirectly by transferring the contents of one

of four associated Data Registers via the XFR Data Register.

1. It is loaded with the contents of its Data Register zero (DR0)

loadings of the R0 value into the WCR. The potentiometer has four 10-bit nonvolatile Data Registers. FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM

WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in progress.
• When WIP = 0, indicates that no high-voltage write cycle is in progress. Device Instructions Identification Byte (ID and A) The first byte sent to the X9111 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9111; this is fixed as 0101[B] (refer to Table 5 on page 6 The A1–A0 bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1–A0 input pins. The slave address is externally specified by the user. The X9111 compares the serial data stream with the address input state; a successful compare of the address bits is required for the X9111 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A1–A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS. The R/W bit is used to set the device to either read or write mode. Instruction Byte and Register Selection The next byte sent to the X9111 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5

TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV) TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 4. IDENTIFICATION BYTE FORMAT

FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 5. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) FIGURE 6. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)

01010 XX X

TABLE 6. INSTRUCTION SET checking the WIP bit (read status register).

10000000 XXXXXX W

1010 R B R A 00XXXXXX W

FN8159 Rev 5.00 Page 9 of 19 October 13, 2016 Write Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE

01010 A 1 A 0

R/ W = 0 1100R B R A00 XXXXXX W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge01010 A 1 A 0 R/ W = 1 1100 R B R A 00 Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE R/ W = 0 1110 R B R A 0 0 Read Status Register (SR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge01010 A 1 A 0 R/ W = 101000001 XXXXXXXX 0000000 W I P NOTES: 4. “A0 and A1”: stand for the device address sent by the master. 5. WCRx refers to wiper position data in the Wiper Counter Register. 6. “X”: Don’t Care.

FN8159 Rev 5.00 Page 10 of 19 October 13, 2016 Absolute Maximum Ratings Recommended Operating Conditions Voltage on SCK any address input Temperature Range Supply Voltage (VCC) Limits CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. Analog Characteristics Over recommended industrial operation conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % Power Rating +25°C, each pot 50 mW IW Wiper Current ±3 mA RW Wiper Resistance Wiper Current = ±50µA, VCC = 5V 40 110 Ω Wiper Current = ±50µA, VCC = 3V 150 300 Ω VTERM Voltage on any RH or RL Pin V SS = 0V V SS VCC V Noise Ref: 1V -120 dBV Resolution 1.6 % Absolute Linearity (Note 7)R w(n)(actual) -Rw(n)(expected), where n = 8 to 1006 ±1 MI ( Note 9) Rw(n)(actual) -Rw(n)(expected) (Note 10) ±1.5 ±2.0 MI ( Note 9) Relative Linearity (Note 8)R w(m + 1) -[Rw(m) + MI], where m = 8 to 1006 ±0.5 MI ( Note 9) Rw(m + 1) -[Rw(m) + MI] (Note 10) ±0.5 ±1.0 MI ( Note 9) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temperature Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitancies See Macro model 10/10/25 pF NOTES: 7. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 8. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 9. MI = RTOT/1023 or (R H – RL)/1023, single pot

FN8159 Rev 5.00 Page 11 of 19 October 13, 2016 DC Operating Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT ICC1 VCC Supply Current (Active) f SCK = 2.5 MHz, SO = Open, VCC = 5.5V Other inputs = VSS 400 µA ICC2 VCC Supply Current (Nonvolatile Write) f SCK = 2.5MHz, SO = Open, VCC = 5.5V Other inputs = VSS 15m A ISB VCC Current (Standby) SCK = SI = V SS, Address = VSS, CS = VCC = 5.5V 3 µA ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V VOL Output LOW Voltage I OH = -1mA, VCC ≥+3V V CC - 0.8 V VOL Output LOW Voltage I OH = -0.4mA, VCC ≤ +3V V CC - 0.4 V Endurance And Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 Years Capacitance SYMBOL TEST TEST CONDITIONS MAX UNIT CIN/OUT (Note 12) Input/Output Capacitance (SI) V OUT = 0V 8 pF COUT (Note 12) Output Capacitance (SO) V OUT = 0V 8 pF CIN (Note 12) Input Capacitance (A0, CS , WP, HOLD, and SCK) V IN = 0V 6 pF Power-Up Timing SYMBOL PARAMETER MIN MAX UNIT tr VCC (Note 12)V CC Power-Up Rate 0.2 50 V/ms tPUR (Note 13) Power-Up to Initiation of Read Operation 1 ms tPUW (Note 13) Power-Up to Initiation of Write Operation 50 ms NOTES: 12. This parameter is not 100% tested. 13. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are not 100% tested. AC Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5

FN8159 Rev 5.00 Page 12 of 19 October 13, 2016 Equivalent AC Load Circuit 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 2714Ω 1382Ω 100pF SO pin 1217Ω AC Timing SYMBOL PARAMETER MIN MAX UNIT fSCK SSI/SPI Clock Frequency 2.5 MHz tCYC SSI/SPI Clock Cycle Time 400 ns tWH SSI/SPI Clock High Time 150 ns tWL SSI/SPI Clock Low Time 150 ns tLEAD Lead Time 150 ns tLAG Lag Time 150 ns tSU SI, SCK, HOLD and CS Input Set-Up Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 50 ns tFI SI, SCK, HOLD and CS Input Fall Time 50 ns tDIS SO Output Disable Time 0 500 ns tV SO Output Valid Time 100 ns tHO SO Output Hold Time 0 ns tRO SO Output Rise Time 50 ns tFO SO Output Fall Time 50 ns tHOLD HOLD Time 400 ns tHSU HOLD Set-Up Time 50 ns tHH HOLD Hold Time 50 ns tHZ HOLD Low to Output in High-Z 100 ns tLZ HOLD High to Output in Low-Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 20 ns tCS CS Deselect Time 100 ns tWPASU WP, A0, A1 Set-Up Time 0 ns tWPAH WP, A0, A1 Hold Time 0 ns

FN8159 Rev 5.00 Page 13 of 19 October 13, 2016 Symbol Table High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNIT tWR High-Voltage Write Cycle Time (Store Instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNIT tWRPO Wiper Response Time after the Third (Last) Power Supply is Stable 5 10 µs tWRL Wiper Response Time after Instruction Issued (All Load Instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

FN8159 Rev 5.00 Page 18 of 19 October 13, 2016 X9111 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE October 13, 2016 FN8159.5 Updated entire datasheet applying Intersil’s new standards. Updated the Ordering Information table on page 2. Updated Notes 1 and 2. Added Note 3. In “AC Timing” on page 12, changed f SCK maximum specification from “2.0” to “2.5”. Added Revision History and About Intersil sections. Updated Package Outline Drawing M14.173 to the latest revision changes are as follows: -Updated drawing to remove table and added land pattern

FN8159 Rev 5.00 Page 19 of 19 October 13, 2016 Package Outline Drawing M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40

0.20 C B A

0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20

1.00 REF

0.65

1.20 MAX

0.25

0.05 MIN

0.15 MAX

(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW For the most recent package outline drawing, see M14.173.