X9111TV14I

X9111 XICOR | Alldatasheet

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REV 1.1.15 5/9/03 Characteristics subject to change without notice. 1 of 21 www.xicor.com X9111 Single Digitally-Controlled (XDCP ) Potentiometer

FEATURES

• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for write, read, and transfer operations of the potentiometer
• Wiper Resistance, 40 Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 3 µ A Max CC : 2.7V to 5.5V Operation
• 100K Ω End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per Register
• 14-Lead TSSOP, 15-Lead CSP (Chip Scale Packaging)
• Low Power CMOS
• Single Supply version of the X9110

DESCRIPTION

The X9111 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 1024-tap / SPI bus A PPLICATION N OTES AND D EVELOPMENT S YSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM RH RL Bus RW Interface & Control POT VCC VSS SPI Bus Address Data Status Write Read Wiper 1024-tapsTransfer NC 100KΩPower On Recall Wiper Counter Register (WCR) Data Registers (DR0-DR3)Control Interface Preliminary Information

– Preliminary Information Characteristics subject to change without notice. 2 of 21REV 1.1.15 5/9/03 www.xicor.com CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems DETAILED FUNCTIONAL DIAGRAM CS SCK SO SI HOLD WP Interface and Control Circuitry VCC VSS DR0 DR1 DR2 DR3 Wiper Counter Register (WCR) RH RL Data RW 1024-taps 100KΩ Control Power On Recall

– Preliminary Information Characteristics subject to change without notice. 3 of 21REV 1.1.15 5/9/03 www.xicor.com PIN CONFIGURATION PIN ASSIGNMENTS Pin (TSSOP) Pin (CSP) Symbol Function

1 A3 SO Serial Data Output

2 B3 A0 Device Address

3 B2, C2 NC No Connect

5 D3 SCK Serial Clock

6 E3 SI Serial Data Input

8D 2 W P Hardware Write Protect

9 E1 A1 Device Address

10 D1 HOLD Device Select. Pause the Serial Bus

11 C1 R

W Wiper Terminal of the Potentiometer

12 B1 R

H High Terminal of the Potentiometer

13 A1 R

L Low Terminal of the Potentiometer

14 A2 V

A B C D E R LVCCSO RHNCA0 RWNCCS HOLDWPSCK A1VSSSI 321

X9111 – Preliminary Information Characteristics subject to change without notice. 4 of 21REV 1.1.15 5/9/03 www.xicor.com PIN DESCRIPTIONS Bus Interface Pins S ERIAL O UTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. S ERIAL I NPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. S ERIAL C LOCK (SCK) The SCK input is used to clock data into and out of the X9111. H OLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. D EVICE A DDRESS , A The address inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input (A1–A0) in order to initiate communication with the X9111. C HIP S ELECT (CS) When CS is HIGH, the X9111 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9111, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. H ARDWARE W RITE P ROTECT I NPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins R H , R L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. R W The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins S YSTEM S UPPLY V OLTAGE CC AND S UPPLY G ROUND SS The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins N O C ONNECT (NC) Pin should be left open. This pin is used for Xicor manufacturing and test purposes. PRINCIPLES OF OPERATION DEVICE DESCRIPTION Serial Interface The X9111 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9111 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 1023 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and R L inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper W ) output. Within the individual array only one switch may be turned on at a time.

Characteristics subject to change without notice. Figure 1. Detailed Potentiometer Block Diagram loadings of the R0 value into the WCR. four Data Registers and the Wiper Counter Register. parameters or user preference data. position (0 ~1023). Table 2. WIP: Write In Progress status bit, read only.

Table 1. Wiper Latch, WL (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V) Table 2. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV) Table 3. Status Register, SR (1-bit) four registers. The format is shown in Table 5. Table 4. Identification Byte Format Table 5. Instruction Byte Format

Figure 3. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers) Figure 4. Four-Byte Instruction Sequence (Read Status Registers)

01010 XX X

Table 6. Instruction Set

110000000 Read the contents of the Wiper

010100000 Write new value to the Wiper

10000000 XXXXXX

10100000 XXXXXX

1010 R B R A 00 XXXXXX

X9111 – Preliminary Information Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status Register (SR) Notes: (1) “A0 and A1”: stand for the device address sent by the master. (2) WCRx refers to wiper position data in the Wiper Counter Register (3) “X”: Don’t Care. CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE

01010 A 1 A 0

R/ W = 0

1100 R B R A 00 XXXXXX

W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge R/ W = 1

1100 R B R A 00

Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE01010 A 1 A 0 R/ W = 0 1110R B R A 0 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge R/ W = 1

01000001 XXXXXXXX 0000000 W I P

X9111 – Preliminary Information ABSOLUTE MAXIMUM RATINGS Voltage on SCK any address input with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended industrial operation conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot (5) ESD Rating on RH, RL, RW pins is 1.5KV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0KV. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % Power Rating 50 mW 25°C, each pot I W Wiper Current ±3 mA RW Wiper Resistance 40 110 Ω Wiper Current = ± 50µA, VCC = 5V 150 300 Ω Wiper Current = ± 50µA, VCC = 3V VTERM Voltage on any RH or RL Pin V SS 5V V SS = 0V Noise -120 dBV Ref: 1V Resolution 1.6 % Absolute Linearity (1) ±1 MI (3) Rw(n)(actual) – Rw(n)(expected), where n=8 to 1006 ±1.5 ±2.0 MI (3) Rw(n)(actual) – Rw(n)(expected) (6) Relative Linearity(2) ±0.5 MI (3) Rw(m + 1) – [Rw(m) + MI], where m=8 to 1006 Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitancies 10/10/25 pF See Macro model RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC) Limits X9111 5V ±10% X9111-2.7 2.7V to 5.5V

X9111 – Preliminary Information D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Notes: (6) This parameter is not 100% tested (7) t PUR and t PUW are the delays required from the time the (last) power supply (V CC-) is stable until the specific instruction can be issued. These parameters are not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 µAf SCK = 2.5 MHz, SO = Open, VCC=5.5V Other Inputs = VSS ICC2 VCC supply current (nonvolatile write) 1 5 mA f SCK = 2.5MHz, SO = Open, VCC=5.5V Other Inputs = VSS ISB VCC current (standby) 3 µA SCK = SI = V SS, Addr. = VSS, CS = VCC = 5.5V ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage –1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOL Output LOW voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOL Output LOW voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. Units Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Symbol Test Max. Units Test Conditions CIN/OUT (6) Input/Output capacitance (SI) 8 pF V OUT = 0V COUT (6) Output capacitance (SO) 8 pF V OUT = 0V CIN (6) Input capacitance (A0, CS, WP, HOLD, and SCK) 6 pF V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC power-up rate 0.2 50 V/ms tPUR (7) Power-up to initiation of read operation 1 ms tPUW (7) Power-up to initiation of write operation 50 ms

X9111 – Preliminary Information A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 Symbol Parameter Min. Max. Units fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle time 400 ns tWH SSI/SPI clock high time 150 ns tWL SSI/SPI clock low time 150 ns tLEAD Lead time 150 ns tLAG Lag time 150 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 50 ns tFI SI, SCK, HOLD and CS input fall time 50 ns tDIS SO output disable time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 50 ns tHH HOLD hold time 50 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 100 ns tWPASU WP, A0, A1 setup time 0 ns tWPAH WP, A0, A1 hold time 0 ns 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel 2714Ω 1382Ω 100pF SO pin 1217Ω

X9111 – Preliminary Information HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 51 0 µ s WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

X9111 – Preliminary Information TIMING DIAGRAMS Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO

X9111 – Preliminary Information XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SI MSB LSB RW tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction)

X9111 – Preliminary Information APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R2R1

X9111 – Preliminary Information Application Circuits (Continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO

X9111 – Preliminary Information Package Dimensions Symbol Millimeters Min Nominal Max Package Width a 2.535 2.565 2.595 Package Length b 3.272 3.302 3.332 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.200 0.220 0.240 Ball Diameter f 0.300 0.320 0.340 Ball Pitch - Width j 0.5 Ball Pitch - Length k 0.5 Ball to Edge Spacing – Width l 0.758 0.783 0.808 Ball to Edge Spacing - Length m 0.626 0.651 0.676 Ball Matrix * True no-connect bump 321 A SO Vcc RL B A0 NC* RH C CS NC* RW D SCK WP HOLD E SI Vss A1 9111TBZ YWW I Lot# 15-Bump Chip Scale Package (CSP B15) Package Outline Drawing a f k mj l b d e c e Top View (Sample Marking) Bottom View (Bumped Side) Side View Side View A3 A2 A1 B3 B2 B1 C3 C2 C1 D3 D2 D1 E3 E2 E1

X9111 – Preliminary Information PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X9111 – Preliminary Information Characteristics subject to change without notice. 21 of 21 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2003 Patents Pending REV 1.1.15 5/9/03 www.xicor.com

ORDERING INFORMATION

Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package V14 = 14-Lead TSSOP B15 = 15-Lead CSP Potentiometer Organization Pot T = 100K Ω X9111 P T V Y