X9111TV14-2.7

X9111 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for Write, Read, And Transfer Operations Of The Potentiometer
• Wiper Resistance, 40 Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 3µA Max CC: 2.7V to 5.5V Operation
• 1 0 0 kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per Register
• 14-Lead TSSOP
• Low Power CMOS
• Single Supply version of the X9110 Pinout Functional Diagram VCC R L VSS 7 8 NC RWCS TSSOP R H SO SI HOLDSCK WP X9111 R H R L Bus R W Interface & Control POT VCC VSS SPI Bus Address Data Status Write Read Wiper 1024-tapsTransfer NC 100kΩPower On Recall Wiper Counter Register (WCR) Data Registers (DR0-DR3)Control Interface Data Sheet March 25, 2005

2 FN8159.1 March 25, 2005 Detailed Functional Diagram Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems CS SCK SO SI HOLD WP Interface and Control Circuitry VCC VSS DR0 DR1 DR2 DR3 Wiper Counter Register (WCR) R H R L Data R W 1024-taps 100kΩ Control Power On Recall X9111

3 FN8159.1 March 25, 2005 Pin Descriptions Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9111. HOLD (HOLD HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0, A1) The address inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input (A1–A0) in order to initiate communication with the X9111. CHIP SELECT (CS When CS is HIGH, the X9111 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9111, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT (NC) Pin should be left open. This pin is used for Intersil manufacturing and test purposes. Principles of Operation Device Description Serial Interface The X9111 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9111 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 1023 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within the individual array only one switch may be turned on at a time. Pin Descriptions PIN (TSSOP) SYMBOL FUNCTION

1 SO Serial Data Output

2 A0 Device Address

3 NC No Connect

5 SCK Serial Clock

6 SI Serial Data Input

8W P Hardware Write Protect

9 A1 Device Address

10 HOLD Device Select. Pause the Serial Bus

11 R W Wiper Terminal of the Potentiometer

12 R H High Terminal of the Potentiometer

13 R L Low Terminal of the Potentiometer

14 V CC System Supply Voltage

select, and enable, one of 1024 switches. contents are lost when the X9111 is powered-down. Registers. These can be read or written directly by the host. operation and will take a maximum of 10ms. WIP: Write In Progress status bit, read only.

• When WIP=1, indicates that high-voltage write cycle is in progress.
• When WIP=0, indicates that no high-voltage write cycle is in progress. Device Instructions Identification Byte (ID and A) The first byte sent to the X9111 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9111; this is fixed as 0101[B] (refer to Table 4). The A1–A0 bits in the ID byte are the internal slave address. The physical device address is defined by the state of the Serial Data Path From Interface Register 0 Serial Bus Input Parallel Bus Input Counter Register RH RL RW 10 10 C O U N T E R D E C O D E If WCR = 000[HEX] then RW = RL If WCR = 3FF[HEX] then RW = RH Wiper (WCR) (DR0) Circuitry Register 1 (DR1) Register 2 (DR2) Register 3 (DR3)

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV) TABLE 3. IDENTIFICATION BYTE FORMAT TABLE 4. INSTRUCTION BYTE FORMAT

TABLE 5. INSTRUCTION SET

01010 XX X

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)

10000000 XXXXXX

10100000 XXXXXX

8 FN8159.1 March 25, 2005 Read Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position (Sent by X9111 on SO) Wiper Position (sent by X9111 on SO) CS Rising Edge 01010A 1A 0 R/ W = 1

1010 R B R A 00XXXXXX

W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R Write Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE

01010 A 1 A 0

R/ W = 0 1100 R B R A 0 0XXXXXX W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge R/ W = 1

1100 R B R A 00

Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE R/ W = 0

1110 R B R A 0 0

Read Status Register (SR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge R/ W = 1

01000001 XXXXXXXX 0000000 WI

P NOTES: 1. “A0 and A1”: stand for the device address sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register 3. “X”: Don’t Care. X9111

9 FN8159.1 March 25, 2005 Absolute Maximum Ratings Recommended Operating Conditions Voltage on SCK any address input Temperature Range Supply Voltage (VCC) Limits CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Analog Characteristics Over recommended industrial operation conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RTOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % Power Rating 25°C, each pot 50 mW IW Wiper Current ±3 mA RW Wiper Resistance Wiper Current = ± 50µA, VCC = 5V 40 110 Ω Wiper Current = ± 50µA, VCC = 3V 150 300 Ω VTERM Voltage on any RH or RL Pin V SS = 0V V SS 5V Noise Ref: 1V -120 dBV Resolution 1.6 % Absolute Linearity (Note 1) R w(n)(actual) -Rw(n)(expected), where n = 8 to 1006 ±1 MI (Note 3) Rw(n)(actual) -Rw(n)(expected) (Note 6) ±1.5 ±2.0 MI (Note 3) Relative Linearity (Note 2) R w(m + 1) -[Rw(m) + MI], where m = 8 to 1006 ±0.5 MI (Note 3) Rw(m + 1) -[Rw(m) + MI] (Note 6) ±0.5 ±1.0 MI (Note 3) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitancies See Macro model 10/10/25 pF NOTES: 1. Absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/1023 or (R H – RL)/1023, single pot X9111

10 FN8159.1 March 25, 2005 D.C. Operating Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS ICC1 VCC supply current (active) fSCK = 2.5 MHz, SO = Open, VCC = 5.5V Other Inputs = VSS 400 µA ICC2 VCC supply current (nonvolatile write) fSCK = 2.5MHz, SO = Open, VCC = 5.5V Other Inputs = VSS 15m A ISB VCC current (standby) SCK = SI = V SS, Addr. = VSS, CS = VCC = 5.5V 3 µA ILI Input leakage current V IN = VSS to VCC 10 µA ILO Output leakage current V OUT = VSS to VCC 10 µA VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage -1 V CC x 0.3 V VOL Output LOW voltage I OL = 3mA 0.4 V VOL Output LOW voltage I OH = -1mA, VCC ≥ +3V V CC - 0.8 V VOL Output LOW voltage I OH = -0.4mA, VCC ≤ +3V V CC - 0.4 V Endurance And Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TEST CONDITIONS MAX UNITS CIN/OUT (Note 6) Input/Output capacitance (SI) V OUT = 0V 8 pF COUT (Note 6) Output capacitance (SO) V OUT = 0V 8 pF CIN (Note 6) Input capacitance (A0, CS , WP, HOLD, and SCK) V IN = 0V 6 pF Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 6) V CC power-up rate 0.2 50 V/ms tPUR (Note 7) Power-up to initiation of read operation 1 ms tPUW (Note 7) Power-up to initiation of write operation 50 ms NOTES: 6. This parameter is not 100% tested. 7. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are not 100% tested. A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X9111

11 FN8159.1 March 25, 2005 Equivalent A.C. Load Circuit 1462Ω 100pF SO pin R H 10pF C L C L R W R TOTAL C W 25pF 10pF R L SPICE Macromodel 2714Ω 1382Ω 100pF SO pin 1217Ω AC Timing SYMBOL PARAMETER MIN MAX UNITS fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle time 400 ns tWH SSI/SPI clock high time 150 ns tWL SSI/SPI clock low time 150 ns tLEAD Lead time 150 ns tLAG Lag time 150 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 50 ns tFI SI, SCK, HOLD and CS input fall time 50 ns tDIS SO output disable time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 50 ns tHH HOLD hold time 50 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 100 ns tWPASU WP, A0, A1 setup time 0 ns tWPAH WP, A0, A1 hold time 0 ns X9111

12 FN8159.1 March 25, 2005 Symbol Table High-voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-voltage write cycle time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9111

13 FN8159.1 March 25, 2005 Timing Diagrams Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO X9111

14 FN8159.1 March 25, 2005 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing Applications information Basic Configurations of Electronic Potentiometers ... CS SCK SI MSB LSB RW tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction) VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current X9111

15 FN8159.1 March 25, 2005 Application Circuits Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO R 2 R 1 VO = (1+R2/R1)VS R 1 R 2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R 2R 1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R 2R 1 X9111

16 FN8159.1 March 25, 2005 Application Circuits (Continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO R 3 R 1 VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R 2R 1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R 2 R 4 R 1 = R2 = R3 = R4 = 10kΩ VS R 2 R 1 R C VO = G VS G = - R2/R1 R 2C 1 R 1 R 3 ZIN – R 2 R 1 R A R B frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9111

17 FN8159.1 March 25, 2005 Packaging Information NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X9111

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8159.1 March 25, 2005

Ordering Information

Blank = 5V ± 10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package V14 = 14-Lead TSSOP Potentiometer Organization Pot T = 100k Ω X9111