X9110TV14I-2.7

X9110_08 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for write, read, and transfer operations of the potentiometer
• Wiper Resistance, 40 Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up
• Standby Current < 3µA Max
• System V CC: 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 1 0 0 kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Dual Supply Version of the X9111
• Low Power CMOS
• Pb-Free Available (RoHS Compliant) Pinout X9110

14 LD TSSOP

INTERFACE & CONTROL POT VCC VSS SPI BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kΩPOWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE Data Sheet February 13, 2008

2 FN8158.3 February 13, 2008 Detailed Functional Diagram

Ordering Information

(V) POTENTIOMETE R RANGE (kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9110TV14 X9110TV 5 ±10 100 0 to +70 14 Ld TSSOP M14.173 X9110TV14Z* (Note) X9110TV Z 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9110TV14I X9110TV I -40 to +85 14 Ld TSSOP M14.173 X9110TV14IZ (Note) X9110TV Z I -40 to +85 14 Ld TSSOP (Pb-free) M14.173 X9110TV14-2.7 X9110TV F 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173 X9110TV14Z-2.7 (Note) X9110TV Z F 0 to +70 14 Ld TSSOP (Pb-free) M14.173 X9110TV14I-2.7 X9110TV G -40 to +85 14 Ld TSSOP M14.173 X9110TV14IZ-2.7* (Note) X9110TV Z G -40 to +85 14 Ld TSSOP (Pb-free) M14.173 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CS SCK SO SI HOLD WP INTERFACE AND CONTROL CIRCUITRY V+VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100kΩ CONTROL POWER ON RECALL X9110

3 FN8158.3 February 13, 2008 Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out on the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9110. HOLD (HOLD HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0) The address input is used to set the 8-bit slave address. A match in the slave address serial data stream A0 must be made with the address input (A0) in order to initiate communication with the X9110. CHIP SELECT (CS When CS is HIGH, the X9110 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9110, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Pin Descriptions PIN (TSSOP) SYMBOL FUNCTION

1 V+ Analog Supply Voltage

2 SO Serial Data Output

3 A0 Device Address

4 SCK Serial Clock

6 SI Serial Data Input

8V - Analog Supply Voltage 9C S Chip Select 10 HOLD Device Select. Pause the Serial Bus

11 R W Wiper Terminal of the Potentiometer

12 R H High Terminal of the Potentiometer

13 R L Low Terminal of the Potentiometer

14 V CC System Supply Voltage

Pin Descriptions (Continued) PIN (TSSOP) SYMBOL FUNCTION X9110

connections on a mechanical potentiometer. supplies set the voltage limits of the potentiometer. The X9110 supports the SPI interface hardware conventions. pins must be HIGH during the entire operation. select, and enable, one of 1024 switches. FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM

proper loadings of the DR0 value into the WCR. Registers. These can be read or written directly by the host. operation and will take a maximum of 10ms. WIP: Write In Progress status bit, read only.

• When WIP = 1, indicates that high-voltage write cycle is in progress.
• When WIP=0, indicates that no high-voltage write cycle is in progress.

TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used To Store The Current Wiper Position (Volatile, V) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)

TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 5. INSTRUCTION BYTE FORMAT this is fixed as 0101[B] (refer to Table 4). the X9110 to successfully continue the command sequence. device address sent by the master executes the instruction.

• Read Wiper Counter Register – read the current wiper position of the selected pot
• Write Wiper Counter Register – change current wiper position of the selected pot
• Read Data Register – read the contents of the selected data register
• Write Data Register – write a new value to the selected data register
• Read Status – This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of t WR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 4). Two instructions require a two-byte sequence to complete (See Figure 2). These instructions transfer data between the host and the X9110; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register
• XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register See Instruction format for more details. ID3 ID2 ID1 ID0 0 0 A0 R/W 0101 (MSB) (LSB) DEVICE TYPE IDENTIFIER INTERNAL SLAVE ADDRESS READ OR WRITE BIT I2 I1 I0 0 RB RA 0 0 (MSB) (LSB) INSTRUCTION OPCODE REGISTER SELECTION RB RA REGISTER DR0 DR1 DR2 DR3 X9110

Status command (See Figure 4). values within 1msec of each other. FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (W RITE OR READ FOR WCR OR DATA REGISTERS)

01010 XX X

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)

TABLE 6. INSTRUCTION SET

10000000 XXXXXX

10100000 XXXXXX

1010 R B R A 00 XXXXXX

9 FN8158.3 February 13, 2008 NOTES: 1. “A0”: stands for the device address sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register 3. “X”: Don’t Care. Write Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE

010100 A 0

R/ W = 0

1100 R B R A0 0XXXXXX

W C R W C R W C R W C R W C R W C R W C R W C R W C R W C R Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge R/ W = 1

1100 R B R A 00

Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge HIGH-VOLTAGE WRITE CYCLE R/ W = 0 1 1 1 0 RB RA 0 0 Read Status Register (SR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge R/ W = 1 010X0001XXXXXXXX0000000 W I P X9110

10 FN8158.3 February 13, 2008 Absolute Maximum Ratings Thermal Information Voltage on SCK any Address Input Thermal Resistance (Typical, Note 4) θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range Supply Voltage (V CC) Limits (Note 8) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications Over recommended industrial (2.7V) operation conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 13) TYP MAX (Note 13) UNITS RTOTAL End to End Resistance 100 k Ω End to End Resistance Tolerance ±20 % Power Rating +25°C, each potentiometer 50 mW IW Wiper Current ±3 mA RW Wiper Resistance Wiper Current = ±3mA, V CC = 3V 150 500 Ω RW Wiper Resistance I W = ±3mA, VCC = 5V 100 Ω Vv+ Voltage on V+ Pin X9110 (Note 8) +4.5 +5.5 V Vv- Voltage on V- Pin X9110 (Note 8) -5.5 -4.5 V VTERM Voltage on any RH or RL Pin V SS = 0V V- V+ V Noise Ref: 1V -120 dBV Resolution 0.1 % Absolute Linearity (Note 5) R w(n)(actual) – Rw(n)(expected), where n = 8 to 1006 ±1 MI (Note 7) Rw(n)(actual) – Rw(n)(expected) (Note 9) ±1.5 MI (Note 7) Relative Linearity (Note 6) R w(m + 1) – [Rw(m) + MI], where m = 8 to 1006 ±0.5 MI (Note 7) Rw(m + 1) – [Rw(m) + MI] (Note 9) ±1 MI (Note 7) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitancies See macro model 10/10/25 pF NOTES: 5. Absolute linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 7. MI = RTOT/1023 or (R H – RL)/1023, single pot 8. V CC, V+, V- must reach their final values within 1ms of each other. X9110

11 FN8158.3 February 13, 2008 D.C. Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 13) TYP MAX (Note 13) UNITS ICC1 VCC Supply Current (active) fSCK = 2.5 MHz, SO = Open, VCC = 5.5V Other Inputs = VSS 400 µA ICC2 VCC Supply Current (nonvolatile write) fSCK = 2.5MHz, SO = Open, VCC = 5.5V Other Inputs = VSS 15m A ISB VCC Current (standby) SCK = SI = V SS, Addr. = VSS, CS = VCC = 5.5V 3µ A ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V VOH Output HIGH Voltage I OH = -1mA, VCC ≥ +3V V CC - 0.8 V VOH Output HIGH Voltage I OH = -0.4mA, VCC ≤ +3V V CC - 0.4 V Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TEST CONDITIONS MAX UNITS CIN/OUT (Notes 8, 10) Input/Output Capacitance (SI) V OUT = 0V 8 pF COUT (Note 10) Output Capacitance (SO) V OUT = 0V 8 pF CIN (Note 10) Input Capacitance (A0, CS , WP, HOLD, and SCK) V IN = 0V 6 pF Power-up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 10) V CC Power-up Rate 0.2 50 V/ms tPUR (Notes 10, 11) Power-up to Initiation of Read Operation 1 ms tPUW (Note 11) Power-up to Initiation of Write Operation 50 ms NOTES: 10. Limits established by characteri zation and are not production tested. 11. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. 13. Parts are 100% tested at +25°C. Over-temperature limi ts established by characterization and are not production tested. A.C. Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5 X9110

12 FN8158.3 February 13, 2008 Equivalent A.C. Load Circuit 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACRO MODEL 2714Ω 2.7V 1382Ω 100pF SO pin 1217Ω AC Timing SYMBOL PARAMETER MIN MAX UNITS fSCK SSI/SPI Clock Frequency 2.0 MHz tCYC SSI/SPI Clock Cycle Time 400 ns tWH SSI/SPI Clock High Time 150 ns tWL SSI/SPI Clock Low Time 150 ns tLEAD Lead Time 150 ns tLAG Lag Time 150 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 50 ns tFI SI, SCK, HOLD and CS Input Fall Time 50 ns tDIS SO Output Disable Time 0 500 ns tV SO Output Valid Time 100 ns tHO SO Output Hold Time 0 ns tRO SO Output Rise Time 50 ns tFO SO Output Fall Time 50 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 50 ns tHH HOLD Hold Time 50 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 20 ns tCS CS Deselect Time 100 ns tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns X9110

13 FN8158.3 February 13, 2008 Symbol Table High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-Voltage Write Cycle Time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper Response Time After the Third (last) Power Supply is Stable 5 10 µs tWRL Wiper Response Time After Instruction Issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9110

14 FN8158.3 February 13, 2008 Timing Diagrams Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB HIGH IMPEDANCE tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO X9110

15 FN8158.3 February 13, 2008 XDCP Timing (For All Load Instructions) Write Protect And Device Address Pins Timing Applications information Basic Configurations Of Electronic Potentiometers ... CS SCK SI MSB LSB RW tWRL ... SO HIGH IMPEDANCE CS WP tWPASU tWPAH (ANY INSTRUCTION) VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current X9110

16 FN8158.3 February 13, 2008 Application Circuits NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9110

17 FN8158.3 February 13, 2008 Application Circuits (continued) ATTENUATOR FILTER INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9110

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8158.3 February 13, 2008 X9110 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06