X90100 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Non-volatile EEPROM storage of programmed trim codes
  • Power On Recall of capacitance setting
  • High-Performance Electronically Trimmable Capacitance
  • Excellent linearity: <0.5 LSB error
  • Very Simple Digital Interface
  • Fast adjustments: 5µs max incremental change
  • Eliminates the need for mechanical tuning
  • Capacitance trimmable from 7.5pF to 14.5pF (single- ended mode)
  • Packages: - MSOP (1.1mm x 3.0mm x 3.0mm)

Applications

  • Post-trim of low-cost regenerative receivers
  • Tunable RF stages
  • Low-cost, Low temperature drift oscillators
  • Garage door openers
  • Keyless entry
  • Industrial wireless control
  • Capacitive sensor trimming
  • RFID tags VCC CS INC U/D N/C Cm Vss Cp

Ordering Information

(°C) X90100M8I 7.5pF to 14.5pF, Single Ended

8 Ld MSOP -40 to +85

X90100M8IT1 7.5pF to 14.5pF, Single Ended

8 Ld MSOP

-40 to +85 Data Sheet February 2, 2005

2 FN8156.0 February 2, 2005 Block Diagram Cm CPAD U/D INC CS VSS CPAD Cp 1*CU 2*CU 4*CU 8*CU 16*CU Logic and E2 Power On ResetVCC Pin Descriptions MSOP SYMBOL BRIEF DESCRIPTION 1I N C Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the capacitance value and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 2U / D Up/Down (U/D). The U/D input controls the direction of the trimmed capacitor value and whether the counter is incremented or decremented. 3V SS Ground. 4C p Cp. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is VSS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS. 5C m Cm. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is VSS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS. 6N / C Not Connected. Must be floating. 7C S Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X90100 will be placed in the low power standby mode until the device is selected once again. 8V CC Positive Supply Voltage. X90100

3 FN8156.0 February 2, 2005 Absolute Maximum Ratings Voltage on CS, INC, U/D, CP, and CAUTION: Stresses above those listed under “Absolute Maximum Rating s” may cause permanent damage to the device. This is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Capacitor Specifications VCC = +5V, TA = 25°C, single ended mode, CM = 0V, unless otherwise stated. SYMBOL PARAMETER TEST CO NDITIONS/NOTES MIN TYP (4) MAX UNIT Absolute accuracy ±15 % VCp Cp terminal voltage 0 V CC V VCm Cm terminal voltage 0 V CC V ∆C Capacitance increments 0.23 pF ∆C Capacitance range 7p F CTOTAL Capacitance at Code=0 7.5 pF CTOTAL Capacitance at Code=31 14.5 pF Q Quality factor (5) f = 315MHz 7 Resolution 5b i t s DNL Relative linearity error (2) ±0.15 lsb TC1 CTOTAL Temperature Coefficient(5) Differential Mode ±50 ppm/°C VCC Supply Voltage 2.7 5.5 V Notes: (1) Absolute linearity is used to determine actual capacitance versus expected capacitance = C(n)(actual) - C(n) (expected) = ±0.15 Ml. (2) Relative linearity is a measure of the error in step size between settings = C(n+1)-[C(n) + Ml] = ±0.15 Ml. (3) lsb = least significant bit = CTOT /31. (4) Typical values are for TA = 25°C and nominal supply voltage. (5) This parameter is not 100% tested. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (4) MAX UNIT ICC1 VCC active current (Increment) CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCYC 50 100 µA ICC2 VCC active current (Store) (EEPROM Store) CS = VIH, U/D = VIL or VIH and INC =V IH @ max. tWR 250 500 µA ISB Standby supply current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V 0.5 2 µA ILI CS, INC, U/D input leakage current V IN = VSS -15 µA VIH CS, INC, U/D input HIGH voltage V CC x 0.7 V CC + 0.5 V VIL CS, INC, U/D input LOW voltage -0.5 V CC x 0.1 V CIN(5) CS, INC, U/D input capacitance V CC = 5V, VIN = VSS, TA = 25°C, f=1 M H z 10 pF X90100

4 FN8156.0 February 2, 2005 AC Timing Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in the CTOTAL output due to a change in the counter value. (7) tIH + tIL ≥ 4µs Endurance and Data Retention VCC = 5V, TA = 25°C unless otherwise specified PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit Data retention 100 Years AC Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V SYMBOL PARAMETER MIN TYP (4) MAX UNIT tCl CS to INC setup 100 ns tlD INC HIGH to U/D change 100 ns tDI U/D to INC setup 100 ns tlL(7) INC LOW period 1 µs tlH(7) INC HIGH period 1 µs tlC INC Inactive to CS inactive 1 µs tCPHNS(5) CS Deselect time (NO STORE) 1 µs tCPHS(5) CS Deselect time (STORE) 10 ms tIW INC to CTOTAL change 1 5 µs tCYC INC cycle time 4 µs tR, tF(5) INC input rise and fall time 500 µs tPU(5) Power up to capacitance stable 5 µs tR VCC(5) VCC power-up rate 0.2 50 V/ms tWR(5) Store cycle 51 0 m s CS INC U/D C TOTAL tCI tIL tIH tCYC tID tIW MI (6) tIC tCPHS tF tR 10% 90% 90% (Store) tDI tCPHNS X90100

5 FN8156.0 February 2, 2005 Power Up Timing (Digital Inputs Floating, Internal Pullup Action Shown) Power Up and Down Requirements There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the Cp, Cm pins provided that VCC is always more positive than or equal to VCp, VCm, i.e., VCC ≥ VCp, VCm. The VCC ramp rate spec is always in effect. Powerup Requirements In order to prevent unwanted tap position changes or an inadvertant store, bring the CS and INC high before or concurrently with the VCC pin. The logic inputs have internal active pullups to provide reliable powerup operation. See powerup timing diagram. Pin Configuration Detailed Pin Descriptions Cp and Cm The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is V SS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS. Up/Down (U/D) The U/D input controls the direction of the trimmed capacitor value and whether the counter is incremented or decremented. This pin has an active current source pullup. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the capacitance value and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. This pin has an active current source pullup. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X90100 will be placed in the low power standby mode until the device is selected once again. This pin has active circuit source pullup. N/C - This pin should be left floating. Principles of Operation There are three sections of the X90100: the input control, counter and decode section; the nonvolatile memory; and the capacitor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on electronic switches connecting internal units to the sum capacitor. Under the proper conditions the contents of the counter can be stored in nonvolatile memory VCC CS INC U/D VCC = 3.3 or 5.0V tRVCC VCC CS INC U/D X90100 MSOP N/C (leave floating) Cm Vss Cp Pin Names SYMBOL DEFAULT DESCRIPTION Cp output Positive capacitor terminal Cm output Negative capacitor terminal VSS supply Ground VCC supply Positive supply voltage U/D pull up Up/Down control input INC pull up Increment control input CS pull up Chip Select control input X90100

6 FN8156.0 February 2, 2005 and retained for future use. The capacitor array is comprised of 31 individual capacitors connected in parallel. At one end of each element is an electronic switch that connects it to the sum. The capacitor, when at either end of the range, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the counter changes positions. If the counter is moved several positions, multiple units are connected to the total for t IW (INC to CTOTAL change). The CTOTAL value for the device can temporarily be increased by a significant amount if the counter is moved several positions. When the device is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the capacitor is set to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the capacitor total value. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty two capacitor combinations for the capacitor array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X90100, move the capacitor value and deselect the device without having to store the latest count total in nonvolatile memory. After the count movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new CTOTAL value will be maintained until changed by the system or until a power- up/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments can be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the counter up and down until the proper trim is attained. Table of Values Mode Selection CS INC U/D MODE L H Cap Value Up L L Cap Value Down H X Store Cap Position H X X Standby Current L X No Store, Return To Standby L H Cap Value Up (not recommended) L L Cap Value Down (not recommended) Single-Ended Mode Differential Mode COUT = Code

  • 7.0 + 7.5 (pF) 0 ≤ Code ≤ 31 COUT = Code • 0.35 + 1.00 (pF) 0 ≤ Code ≤ 31 C p C m X90100 Oscillator Circuit C p C m X90100 Oscillator Circuit C p C s Example of a single-ended circuit Example of a differential mode circuit X90100

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8156.0 February 2, 2005 Packaging Information 0.118 ± 0.002 (3.00 ± 0.05) 0.040 ± 0.002 (1.02 ± 0.05) 0.150 (3.81) Ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7° Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 8-Lead Miniature Small Outline Gull Wing Package Type M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 0.220" 0.0256" Typical 0.025" Typical 0.020" Typical

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Ref. X90100