X84256 XICOR | Alldatasheet

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Technical content

Ó Xicor, Inc. 1998 Patents Pending 4005 1 8/24/99 WW Characteristics subject to change without notice 256K MPS Ô EEPROM µPort Saver EEPROM

FEATURES

  • Up to 10MHz data transfer rate
  • 25ns Read Access Time
  • Direct Interface to Microprocessors and Microcontrollers —Eliminates I/O port requirements —No interface glue logic required —Eliminates need for parallel to serial converters
  • Low Power CMOS —2.5V–5.5V and 5V ±10% Versions —Standby Current Less than 1µA —Active Current Less than 3mA
  • Byte or Page Write Capable —64-Byte Page Write Mode
  • Typical Nonvolatile Write Cycle Time: 2ms
  • High Reliability —1,000,000 Endurance Cycles —Guaranteed Data Retention: 100 Years
  • Small Packages Options —8, 16-Lead SOIC Packages —14-Lead TSSOP Packages —8-Lead XBGA Packages

DESCRIPTION

The µPort Saver memories need no serial ports or spe- cial hardware and connect to the processor memory bus. Replacing bytewide data memory, the µPort Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µPort Saver provides all the serial benefits, such as low cost, low power, low volt- age, and small package size while releasing I/Os for more important uses. The µPort Saver memory outputs data within 25ns of an active read signal. This is less than the read access time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With rates to 10 MHz, the µPort Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs. The µPort Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This “bit serial” interface allows the µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems. A Write Protect (WP ) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applica- tions requiring extended endurance. Inherent data reten- tion is greater than 100 years. BLOCK DIAGRAM CE I/O H.V. GENERATION TIMING & CONTROL EEPROMCOMMAND DECODE AND CONTROL LOGIC X DEC Y DECODE DATA REGISTER WP OE WE ARRAY 32K x 8 P0/CS P1/CLK P2/DI P3/DO System Connection Internal Block Diagram µP µC Ports Saved DSP ASIC A15 OE WE MPS RISC X84256

Drawings are to the same scale, actual package sizes are shown in inches: PIN NAMES PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is dese- lected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. Output Enable (OE The Output Enable input must be LOW to enable the out- put buffer and to read data from the device on the I/O line. Write Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the device. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the device through the I/O pin. Write Protect (WP) When the Write Protect input is LOW, nonvolatile writes to the device are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a nonvol- atile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. DEVICE OPERATION The X84256 serial EEPROM is designed to interface directly with most microprocessor buses. Standard CE OE , and WE signals control the read and write opera- tions, and a single l/O line is used to send and receive data and commands serially. V CC NC OE WE CE I/O WP VSS 8-LEAD SOIC 14-LEAD TSSOP I/O WP VSS NC OE WE NC V CC NC CE NC NC NC NC I/O CE OE WP VCC NC WE VSS 8-LEAD XBGA X84256 16-LEAD SOIC I/O NC VSS NC OE WE NC V CC NC CE NC NC NC NC WP NC I/O Data Input/Output CE Chip Enable Input OE Output Enable Input WE Write Enable Input WP Write Protect Input V CC Supply Voltage V SS Ground NC No Connect

the l/O line is active whenever both OE and CE are LOW. never both LOW while CE is LOW. read sequentially by continuing to issue read cycles. may be continued indefinitely. time to interrupt or end a sequential read or page load. Figure 1. Read Sequence

  • an illegal sequence is entered. The following are the more common illegal sequences: —Read/Write/Write—any time —Read/Write ‘1’—When writing the address or writ- ing data.

Figure 2. Write Sequence

—Write ‘1’—when reading data —Read/Read/Write ‘1’—after data is written to device, but before entering the NV write sequence. —the device powers-up; —a nonvolatile write operation completes. While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest power condition, an invalid condition is created by writing a ‘1’ after the last bit of a read operation. Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: —A special “start nonvolatile write” command sequence is required to start a nonvolatile write cycle. ABSOLUTE MAXIMUM RATINGS* Terminal Voltage with Respect to V SS RECOMMENDED OPERATING CONDITIONS *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C Military† –55°C +125°C Supply Voltage Limits X84256 5V 10% X84256 – 2.5 2.5V to 5.5V X84256 – 1.8 1.8V to 3.6V D.C. OPERATING CHARACTERISTICS (V CC = 5V 10%) (Over the recommended operating conditions, unless otherwise specified.) Notes: (1) V IL Min. and V IH Max. are for reference only and are not tested. Symbol Parameter Limits Units Test ConditionsMin. Max. I CC1 V CC Supply Current (Read) 1 mA OE = V IL , WE = V IH I/O = Open, CE clocking @ 10MHz I CC2 V CC Supply Current (Write) 3m A I CC During Nonvolatile Write Cycle All Inputs at CMOS Levels I SB1 V CC Standby Current 1 m A CE = V CC , Other Inputs = V CC or V SS I LI Input Leakage Current 10 m A V IN = V SS to V CC I LO Output Leakage Current 10 m A V OUT = V SS to V CC V lL (1) Input LOW Voltage –0.5 V CC x 0.3 V V IH (1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V V OL Output LOW Voltage 0.4 V I OL = 2.1mA V OH Output HIGH Voltage V CC – 0.8 V I OH = –1mA

D.C. OPERATING CHARACTERISTICS (V CC = 2.5V to 5.5V) (Over the recommended operating conditions, unless otherwise specified.) D.C. OPERATING CHARACTERISTICS (V CC = 1.8V to 3.6V) (Over the recommended operating conditions, unless otherwise specified.) Notes: (1) V IL Min. and V IH Max. are for reference only and are not tested. Symbol Parameter Limits Units Test ConditionsMin. Max. I CC1 VCC Supply Current (Read) 1m A OE = VIL, WE = VIH, I/O = Open, CE clocking @ 5MHz ICC2 VCC Supply Current (Write) 3m A ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB1 VCC Standby Current 1µ A CE = VCC , Other Inputs = VCC or VSS ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VlL (1) Input LOW Voltage –0.5 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 1mA, VCC = 3V VOH Output HIGH Voltage VCC – 0.4 V IOH = –400mA, VCC = 3V Symbol Parameter Limits Units Test ConditionsMin. Max. ICC1 VCC Supply Current (Read) 500 µA OE = VIL, WE = VIH, I/O = Open, CE clocking @ 3MHz ICC2 VCC Supply Current (Write) 2m A ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB1 VCC Standby Current 1µ A CE = VCC , Other Inputs = VCC or VSS ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VlL (1) Input LOW Voltage –0.5 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 0.5mA, VCC = 2V VOH Output HIGH Voltage VCC – 0.2 V IOH = –250mA, VCC = 2V

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Notes: (2) Periodically sampled, but not 100% tested. POWER-UP TIMING Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested. A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUITS Symbol Parameter Max. Units Test Conditions C I/O (2) Input/Output Capacitance 8 pF VI/O = 0V C IN (2) Input Capacitance 6 pF VIN = 0V Symbol Parameter Max. Units tPUR (3) Power-up to Read Operation 2 ms tPUW (3) Power-up to Write Operation 5 ms Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 5ns Input and Output Timing Levels V CC x 0.5 30pF 2.06KW 3.03KW OUTPUT

7008 FRM F06

2.39KW 4.58KW OUTPUT

7008 FRM F07

2.8KW 5.6KW OUTPUT

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits – X84256 Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load. Symbol Parameter VCC = 5V±10% V CC = 2.5V – 5.5V VCC = 1.8V – 3.6V tRC Read Cycle Time 100 200 330 ns tCE CE Access Time 25 50 70 ns tOE OE Access Time 25 50 70 ns tOEL OE Pulse Width 50 60 90 ns tOEH OE High Recovery Time 50 60 90 ns tLOW CE LOW Time 50 70 90 ns tHIGH CE HIGH Time 50 120 180 ns tLZ (4) CE LOW to Output In Low Z 0 0 0 ns tHZ (4) CE HIGH to Output In High Z 0 25 0 30 0 35 ns tOLZ (4) OE LOW to Output In Low Z 0 0 0 ns tOHZ (4) OE HIGH to Output In High Z 0 25 0 30 0 35 ns tOH Output Hold from CE or OE HIGH 0 0 0 ns tWES WE HIGH Setup Time 25 25 25 ns tWEH WE HIGH Hold Time 25 25 25 ns CE WE tWES OE tHIGH tCE tOE tOLZ tOH tWEH HIGH ZDATA tOHZ tHZtLZ tLOW tRC I/O OELt tOEH

Write Cycle Limits – X84256 Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle” sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84256 on the rising edge of CE or WE, whichever occurs first. (7) Periodically sampled, but not 100% tested. Symbol Parameter VCC = 5V ±10% V CC = 2.5V – 5.5V VCC = 1.8V – 3.6V Units tNVWC (5) Nonvolatile Write Cycle Time 5 5 5 ms tWC Write Cycle Time 100 200 330 ns tWP WE Pulse Width 25 40 70 ns tWPH WE HIGH Recovery Time 65 150 200 ns tCS Write Setup Time 0 0 0 ns tCH Write Hold Time 0 0 0 ns tCP CE Pulse Width 25 40 70 ns tCPH CE HIGH Recovery Time 65 150 200 ns tOES OE HIGH Setup Time 25 25 50 ns tOEH OE HIGH Hold Time 25 25 50 ns tDS (6) Data Setup Time 12 20 30 ns tDH (6) Data Hold Time 5 5 5 ns tWPSU (7) WP HIGH Setup 100 100 150 ns tWPHD (7) WP HIGH Hold 100 100 150 ns

NOTE: ALL DIMENSIONS IN mM B e D D E E X84256: Bottom View ALL DIMENSIONS ARE TYPICAL VALUES C I/O CE VSS WP VCC NC WE OE A

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 16-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.030" Typical

16 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 0.050" Typical

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

ORDERING INFORMATION

Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C VCC Range Blank = 4.5V to 5.5V, 10 MHz 2.5 = 2.5V to 5.5V, 5 MHz Military = –55°C to +125°C (contact factory) Packages: X84256 S8 = 8-Lead SOIC S16 = 16-Lead SOIC V14 = 14-Lead TSSOP Z = 8-Lead XBGA 14-Lead TSSOP YWW 84256 F = 2.5 to 5.5V, 0 to +70°C G = 2.5 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C 8-Lead SOIC X84256 X XX Blank = 8-Lead SOIC F = 2.5 to 5.5V, 0 to +70°C G = 2.5 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. *PART MARK CONVENTION 8-Lead XBGA Complete Part Number Top Mark X84256Z–2.5 X84256ZI–2.5 XABA XABB 1.8 = 1.8V to 3.6V, 3MHz (contact factory)