X84041 XICOR | Alldatasheet
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Technical content
4K X84041 MPS ™ E2PROM
DESCRIPTION
The X84041 Micro Port Saver is a 4096-bit CMOS E2PROM designed for a direct interface to port limited microcontroller or I/O limited microprocessor designs. The X84041 provides all of the benefits of serial memo- ries, such as low cost, low power, low voltage operation, and small package size, while featuring higher data transfer rates and reduced interface code requirements— without the need for a dedicated serial bus. The X84041 is organized as a 512 x 8, but is also suitable in 16-bit or 32-bit environments, due to the bit serial nature of the interface. The X84041 directly connects to the processor bus and communicates over a single data line using a sequence of standard bus read and write operations. This elimi- nates the need for dedicated port pins, parallel to serial converters, complicated ASIC implementations, or other glue logic, lowering system cost.
FEATURES
- Direct Interface to Micros —Eliminates I/O port requirements —No interface glue logic required —Eliminates need for parallel to serial converters
- 3.3Mbps data transfer rate
- Low Power CMOS —2.7V to 5.5V Operation —Standby Current Less than 50 µA —Active Current Less than 1mA
- 45ns Read Access Time
- 8-Byte Page Write Mode
- Typical Nonvolatile Write Cycle Time: 5ms
- High Reliability —100,000 Endurance Cycles —Guaranteed Data Retention: 100 Years
- 8-Lead PDIP, 8-Lead SOIC, and 14-Lead TSSOP Packages © Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 2704-4.4 6/12/96 T3/C1/D0 NS CE I/O H.V. GENERATION TIMING & CONTROL EEPROM ARRAY 512 x 8 COMMAND DECODE AND CONTROL LOGIC X DEC Y DECODE DATA REGISTER WP
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PIN CONFIGURATION BLOCK DIAGRAM A PPLICA TION NOTES AND DEVELOPMENT SYSTEM A V AILABLE AN10 • AN17 • AN57 • XK84 VCC NC OE WE 2704 ILL F01.2 CE I/O WP VSS X84041 DIP/SOIC 2704 ILL F02a.1 TSSOP X84041 CE I/O NC NC NC WP V SS VCC NC NC NC NC OE WE
A Write Protect (WP) pin provides hardware protection against inadvertent writes to the memory. Xicor E2PROMs are designed and tested for applica- tions requiring extended endurance. Inherent data re- tention is greater than 100 years. PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is dese- lected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the X84041 is in the standby power mode. Output Enable (OE) The Output Enable input must be LOW to enable the output buffer and to read data from the X84041 on the I/O line. Write Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the X84041. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the X84041 through the I/O pin. Write Protect (WP) When the Write Protect input is LOW, nonvolatile writes to the X84041 are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a nonvolatile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. DEVICE OPERATION The X84041 is a serial 512 x 8 bit E 2PROM designed to interface directly with most microprocessor buses. Stan- dard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle be- tween the write cycles. The address is sent serially, most significant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restric- tions, and the processor is free to perform other tasks on the bus whenever the X84041 CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, issuing a reset sequence will terminate the read sequence, otherwise the X84041 will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address is reached ($1FF), the ad- dress counter rolls over to address $000 and reading may be continued indefinitely. Reset Sequence The reset sequence resets the X84041 and sets an internal write enable latch. A reset sequence can be sent at any time by performing a read/write “0”/read se- quence (see Figs. 1 and 2). This sequence breaks the multiple read or write cycle sequences that are normally used when reading from or writing to the part. This sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write “0” cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the X84041 initiates these operations properly.
Figure 1. Read Sequence
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Sequence section) to set the internal write enable latch.
Figure 2. Write Sequence
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write enable latch before starting a write sequence. at the end of a nonvolatile write cycle.
D.C. OPERATING CHARACTERISTICS (V CC = 5V ±10%) (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA OE = VIL, WE = VIH, I/O = Open, CE clocking @ 2MHz ICC2 VCC Supply Current (Write) 3 mA I CC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB VCC Standby Current 50 µA CE = VCC , Other Inputs = VCC or VSS VCC = 5V ±10% ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VlL (1) Input LOW Voltage –1 V CC x 0.3 V VIH (1) Input HIGH Voltage V CC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 2.1mA, VCC = 5V ±10% VOH Output HIGH Voltage V CC – 0.8 V I OH = –1mA, VCC = 5V ±10% 2704 PGM T04.3 *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Terminal Voltage with Respect to V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C 2704 PGM T02.2 † Contact factory for availability. Supply Voltage Limits X84041 5V ±10% X84041 – 3 3V ±10% X84041 – 2.7† 2.7V to 5.5V 2704 PGM T03.2
D.C. OPERATING CHARACTERISTICS (V CC = 3V ±10%) (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 250 µA OE = VIL, WE = VIH, I/O = Open, CE clocking @ 2MHz ICC2 VCC Supply Current (Write) 1 mA I CC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB1 VCC Standby Current 10 µA CE = VCC , Other Inputs = VCC or VSS VCC = 3V ±10% ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VlL(1) Input LOW Voltage –1 V CC x 0.3 V VIH(1) Input HIGH Voltage V CC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 1mA, VCC = 3V ±10% VOH Output HIGH Voltage V CC – 0.4 V I OH = –400µA, VCC = 3V ±10% 2704 PGM T05.2 Notes: (2) Periodically sampled, but not 100% tested. POWER-UP TIMING Symbol Parameter Max. Units tPUR (3) Power-up to Read Operation 2 ms tPUW (3) Power-up to Write Operation 5 ms
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A.C. CONDITIONS OF TEST Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 5ns Input and Output V CC x 0.5 Timing Levels 2704 PGM T08.1 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions C I/O(2) Input/Output Capacitance 8 pF V I/O = 0V C IN(2) Input Capacitance 6 pF V IN = 0V 2704 PGM T06.2 Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load. A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits – X84041 V CC = 5V ±10% V CC = 3V ±10% Symbol Parameter Min. Max. Min. Max. Units tRC Read Cycle Time 300 300 ns tCE CE Access Time 45 65 ns tOE OE Access Time 45 65 ns tLOW CE LOW Time 70 70 ns tHIGH CE HIGH Time 70 70 ns tLZ(4) CE LOW to Output In Low Z 0 0 ns tHZ (4) CE HIGH to Output In High Z 0 30 0 35 ns tOLZ (4) OE LOW to Output In Low Z 0 0 ns tOHZ (4) OE HIGH to Output In High Z 0 30 0 35 ns tOH Output Hold from CE or OE HIGH 0 0 ns tWES WE HIGH Setup Time 25 25 ns tWEH WE HIGH Hold Time 25 25 ns 2704 PGM T09.3 30pF 2.06KΩ 3.03KΩ OUTPUT 2704 ILL F05.2 30pF 2.39KΩ 4.58KΩ OUTPUT 2704 ILL F05a.3
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Write Cycle Limits – X84041 VCC = 5V ±10% V CC = 3V ±10% Symbol Parameter Min. Max. Min. Max. Units tNVWC (5) Nonvolatile Write Cycle Time 10 10 ms tWC Write Cycle Time 300 300 ns tWP WE Pulse Width 30 30 ns tWPH WE HIGH Recovery Time 200 200 ns tCS Write Setup Time 0 0 ns tCH Write Hold Time 0 0 ns tCP CE Pulse Width 30 30 ns tCPH CE HIGH Recovery Time 200 200 ns tOES OE HIGH Setup Time 50 50 ns tOEH OE HIGH Hold Time 50 50 ns tDS (6) Data Setup Time 30 30 ns tDH (6) Data Hold Time 5 5 ns tWPCS (7) WP HIGH Before CE 500 500 ns tWPCH (7) WP HIGH After CE 500 500 ns tWPWS (7) WP HIGH Before WE 500 500 ns tWPWH (7) WP HIGH After WE 500 500 ns 2704 PGM T10.3Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle” sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84041 on the rising edge of CE or WE, whichever occurs first. (7) Periodically sampled, but not 100% tested.
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NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL
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NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .193 (4.9) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)
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Blank = 4.5V to 5.5V 3 = 2.7V to 3.3V 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC V = 14-Lead TSSOP X84041 X X -X LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.