X80140Q20I

X80140 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• Quad Voltage Monitor and Sequencing - Four independent voltage monitors - Four time delay circuits (in circuit programmable) - Remote delay via SMBus - Factory programmable voltage thresholds - Sequence up to 5 power supplies.
• Fault Detection Register - Remote diagnostics of voltage fail event.
• Debounced Manual Reset Input
• Manufacturing/Configuration Memory - 2Kbits of EEPROM - 400kHz SMBus interface
• Available Packages - 20-lead Quad No-Lead Frame (QFN - 5x5mm)

Applications

• General Purpose Timers
• Long Time Delay Generation
• Cycle Timers / Waveform Generation
• ON/OFF Delay Timers
• Supply Sequencing for Distributed Power
• Programmable Delay Event Sequencing
• Multiple DC-DC ON/OFF Sequencing
• Voltage Window Monitoring with Reset
• ON/OFF Switches with Programmable Delay
• Voltage Supervisor with Programmable Output Delays
• Databus Power Sequencing
• 100 ms to 5 secs Sele ctable Delay Switches
• ATE or Data Acquisition Timing Applications
• Datapath/Memory Timing Applications
• Data Pipeline Timing Applications
• Batch Timer/Sequencers
• Adjustable Duty Cycle Applications V1GDO MR NC V3GDO V2GDO V4MON V3MON V1MON RESET WPV4GDO SCL 181920 V2MON (5mm x 5mm) 91 0 VP DNC SDA VCC VSS

Ordering Information

NUMBER V REF1 VREF2 VREF3 VREF4 PACKAGE X80140Q20I 4.5 3.0 2.25 0.9 QFN X80141Q20I 4.5 2.25 0.9 0.9 QFN X80142Q20I 3.0 2.25 1.7 0.9 QFN X80143Q20I 3.0 2.25 0.9 0.9 QFN X80144Q20I 2.25 2.25 0.9 0.9 QFN Data Sheet January 20, 2005

2 FN8153.0 January 20, 2005 Block Diagram MR V1MON V2MON V3MON V4MON V4GDO V3GDO V2GDO V1GDO WP SCL SDA RESET VP EEPROM 2kbits VMON LOGIC VCC BUS INTERFACE VSS VSS VREF1 VREF2 VREF3 VREF4 POR CONTROL AND FAULT REGISTERS VSS DIVIDER RESET LOGIC AND DELAY VSS Reset OSC 0.1s 0.5s Select delay1 delay2 delay3 delay4 Delay circuit repeated 4 times X80140, X80141, X80142, X80143, X80144

3 FN8153.0 January 20, 2005 Absolute Maximum Ratings Recommended Operating Conditions ViGDO V V CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications (Standard Setting) Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS VCC Supply Operating Range 4.5 5.5 V ICC Supply Current f SCL = 0kHz 1.0 2.5 mA VP (Note 3) EEPROM programming voltage 9 12 V IP Programming Current 10 mA ILI Input Leakage Current (MR) V IL = GND to VCC 10 µA ILO Output Leakage Current (V1GDO, V2GDO, V3GDO, V4GDO, RESET) 15 µA VIL Input LOW Voltage (MR) -0.5 V CC x 0.3 V VIH Input HIGH Voltage (MR) V CC x 0.7 5.5 V VOL Output LOW Voltage (RESET, V1GDO, V2GDO, V3GDO, V4GDO) IOL = 4.0mA 0.4 V COUT (Note 1) Output Capacitance (RESET, V1GDO, V2GDO, V3GDO, V4GDO) VOUT = 0V 8 pF VREF1 V1MON Trip Point Voltage (Range) 2.20 4.70 V X80140 4.45 4.50 4.55 V X80141 4.45 4.50 4.55 V X80142 2.95 3.00 3.05 V X80143 2.95 3.00 3.05 V X80144 2.20 2.25 2.30 V V REF2 V2MON Trip Point Voltage 2.20 4.70 V X80140 2.95 3.00 3.05 V X80141 2.20 2.25 2.30 V X80142 2.20 2.25 2.30 V X80143 2.20 2.25 2.30 V X80144 2.20 2.25 2.30 V X80140, X80141, X80142, X80143, X80144

4 FN8153.0 January 20, 2005 Equivalent A.C. Output Load Circuit VREF3 V3MON Trip Point Voltage 0.85 3.50 V X80140 2.20 2.25 2.30 V X80141 0.85 0.90 0.95 V X80142 1.65 1.70 1.75 V X80143 0.85 0.90 0.95 V X80144 0.85 0.90 0.95 V V REF4 V4MON Trip Point Voltage 0.85 3.50 V All Devices 0.85 0.90 0.95 V VREF Voltage Reference Long Term Drift 10 years 0 -100 mV AC CHARACTERISTICS tMR (Note 3) Minimum time high for reset valid on the MR pin 5 µs tMRE (Note 3) Delay from MR enable to V1GDO HIGH 1.6 µs tDPOR (Note 3) Internal Device Delay on power up 45 50 55 ms tTO (Note 3) ViGDO turn off time 50 ns Electrical Specifications (Standard Setting) Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Specifications (Programmable Parameters) Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSPOR Delay before RESET assertion TPOR1 = 0 TPOR0 = 0 Factory Default 90 100 110 ms TPOR1 = 0 TPOR0 = 1 (Note 3) 450 500 550 ms TPOR1 = 1 TPOR0 = 0 (Note 3) 0.9 1 1.1 s TPOR1 = 1 TPOR0 = 1 (Note 3) 4.5 5 5.5 s t DELAYi Time Delay used in Power Sequencing (i = 1 to 4) TiD1 = 0 TiD0 = 0 Factory Default 90 100 110 ms TiD1 = 0 TiD0 = 1 (Note 3) 450 500 550 ms TiD1 = 1 TiD0 = 0 (Note 3) 0.9 1 1.1 s TiD1 = 1 TiD0 = 1 (Note 3) 4.5 5 5.5 s SDA 30pF 4.6kΩ RESET 30pF V1GDO , 4.6kΩ 30pF V2GDO , V3GDO , V4GDO 4.6kΩ A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load X80140, X80141, X80142, X80143, X80144

6 FN8153.0 January 20, 2005 Serial Interface Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS ICC1 Active Supply Current (VCC) Read or Write to Memory or registers VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz 2.5 mA ILI Input Leakage Current (SCL, WP, A0, A1) V IL = GND to VCC 15 µA ILO Output Leakage Current (SDA) V SDA = GND to VCC Device is in Standby 15 µA VIL Input LOW Voltage (SDA, SCL, WP , A0, A1) -0.5 V CC x 0.3 V VIH Input HIGH Voltage (SDA, SCL, WP, A0, A1) V CC x 0.7 5.5 V VHYS Schmidt Trigger Input Hysteresis Fixed input level 0.2 V VCC related level 0.05 x 5 V VOL Output LOW Voltage (SDA) I OL = 4.0mA 0.4 V AC CHARACTERISTICS fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA (Note 1) SCL LOW to SDA Data Out Valid 0.1 1.5 µs tBUF (Note 1) Time the bus is free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tHD:STO Stop Condition Hold Time 0.6 µs tDH (Note 1) Data Output Hold Time 50 ns tR (Note 1) SDA and SCL Rise Time 20 +.1Cb 300 ns tF (Note 1) SDA and SCL Fall Time 20 +.1Cb 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs tSU:ADR A0, A1 Setup Time 0.6 µs tHD:ADR A0, A1 Hold Time 0 µs tSU:VP VP Setup Time 0.6 µs Cb (Note 3) Capacitive load for each bus line 400 pF tWC (Note 2) EEPROM Write Cycle Time 5 10 ms NOTES: 1. This parameter is based on characterization data. 2. t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is not 100% tested. X80140, X80141, X80142, X80143, X80144

8 FN8153.0 January 20, 2005 Pin Configuration X80140/1/2/3/4 V1GDO MR NC V3GDO V2GDO V4MON V3MON V1MON RESET WPV4GDO SCL 181920 V2MON (5mm x 5mm) 91 0 VP DNC SDA VCC VSS Pin Descriptions PIN NAME DESCRIPTION 1V 4 G D O V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4 and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin. 2V 4 M O N V4 Voltage Monitor Input. Fourth voltage monitor pin. If unused connect to VCC. 3V 3 G D O V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than VREF3 and goes LOW when V3MON is greater than VREF3. There is user selectable delay circuitry on this pin. 4V 3 M O N V3 Voltage Monitor Input. Third voltage monitor pin. If unused connect to VCC. 5V 2 G D O V2 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V2MON is less than VREF2 and goes LOW when V2MON is greater than VREF2. There is user selectable delay circuitry on this pin. 6V P EEPROM programming Voltage. 7V 2 M O N V2 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC. 8 DNC Do Not Connect. 9 A1 Address Select Input. It has an internal pull-down resistor. (>10M Ω typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface. 10 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 11 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 12 V1MON V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC. 13 V1GDO V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1 and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin. 14 RESET RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and the power sequencing is complete. This pin will be released after a programmable delay. 15 WP Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the device. It has an internal pull-down resistor. (>10MΩ typical) 16 MR Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an internal pull-down resistor. (>10MΩ typical) 17 V SS Ground Input. 18 NC No Connect. No internal connections. 19 A0 Address Select Input. It has an internal pull-down resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface. 20 V CC Supply Voltage. X80140, X80141, X80142, X80143, X80144

• It prevents the processor from operating prior to stabilization of the oscillator.
• It allows time for an FPGA to download its configuration prior to initialization of the circuit.
• It prevents communicat ion to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior to system initialization. The POR/RESET circuit is activated when all voltages are within specified ranges and the V1GDO , V2GDO, V3GDO, and V4GDO time-out conditions are met. The POR/RESET circuit will then wait tSPOR and de-assert the RESET pin. The POR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100ms, 500ms, 1 second, or 5 seconds. Manual Reset The manual reset option allows a hardware reset of the power sequencing pins. These can be used to recover the system in the event of an abnormal operating condition. Activating the MR pin for more than 5us sets all of the ViGDO outputs and the RESET output active (LOW). When MR is released (and if all supplies are still at their proper operating voltage) then the ViGDO and RESET pins will be released after their programmed delay periods. (See Figure 3.) Quad Voltage Monitoring X80140 monitors 4 voltage inputs. When the ViMON (i=1-4) input is detected to be above the input threshold, the output ViGDO (i = 1 to 4) goes inactive (LOW). The ViGDO signal is de-asserted after a delay of 100ms. This delay can be changed on each ViGDO output individually with bits in register CR3. The delay can be 100ms, 500ms, 1s and 5s. Each ViGDO signal remains active until its associated ViMON input rises above the threshold. Fault Detection The X80140 contains a Fault Detection Register (FDR) that provides the user the status of the causes for a RESET pin active (See Table 20). At power-up, the FDR is defaulted to all “0”. The system needs to initialize the register to 0Fh before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register changes from a “1” to a “0” to indicate the failure. When a RESET is detected by the main controller, the controller should read the FDR and note the cause of the fault. After reading the register, the controller can reset the register bit back to all “1” in preparation for future failure conditions. Flexible Power Sequencing of Multiple Power Supplies The X80140 provides several circuits such as multiple voltage monitors, programmable delays, and output drive signals that can be used to set up flexible power monitoring or sequencing schemes system power supplies. Below are two examples: 1. Power Up of Supplies In Parallel Using Programmable Delays. (See Figure 7 and Figure 8). 2. The X80140 monitors several power supplies, powered by the same source voltage, that all begin power up at the same time. Each voltage source is fed into the ViMON inputs to the X80140. The ViMON inputs monitor the voltage to make sure it has reached the minimum desired level. When each voltage monitor determines that its input is good, a counter starts. After the programmed delay time, the X80140 sets the ViGDO signals LOW. Any individual voltage failure can be viewed in the Fault Detection Register. 3. In the factory default condition, each ViGDO output is instructed to go LOW 100ms after the input voltage reaches its threshold. However, each ViGDO delay is individually selectable as 100ms, 500ms, 1s and 5s. The delay times are changed via the SMBus during calibration of the system.

TABLE 1. POR RESET DELAY OPTIONS TABLE 2. VIGDO OUTPUT TIME DELAY OPTIONS where i is the specific voltage monitor (i = 1 to 4).

• Control Register (CR)
• Fault Detection Register (FDR)
• EEPROM array Registers The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. EEPROM Array The X80140 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Register and Memory Protection In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80140. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin. WEL: Write Enable Latch A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80140. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Note, a write to FDR does not require that WEL=1. BP1 and BP0: Block Protect Bits The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array. WPEN: Write Protect Enable The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, and CR) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that is not block protected can be written. Non Volatile Programming Voltage (VP) Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation. BP1 BP0 PROTECTED ADDRESSES (SIZE) ARRAY LOCK 0 0 None (Default) None (Default) 0 1 C0h - FFh (64 bytes) Upper 1/4 1 0 80h - FFh (128 bytes) Upper 1/2 1 1 00h - FFh (256 bytes) All

TABLE 3. WRITE PROTECT CONDITIONS

TABLE 4. REGISTER ADDRESS MAP

0000 V 4 0 S V 3 0 S V 2 0 S V 1 0 S V o l a t i l e

TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY WEL = 0 prevents write operations. CR1 4:3 BP1=0, BP0=0 : No EEPROM memory protected. BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected. 1st Voltage Monitor V1OS FDR 0 V1OS = 0 : V1GDO pin has been asserted (must be preset to 1). 2nd Voltage Monitor V2OS FDR 1 V2OS = 0 : V2GDO pin has been asserted (must be preset to 1). 3rd Voltage Monitor V3OS FDR 2 V3OS = 0 : V3GDO pin has been asserted (must be preset to 1). 4th Voltage Monitor V4OS FDR 3 V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).

• The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted.
• The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers.
• The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 13). Serial Write Operations Before any write operations can be performed, a programming supply voltage (VP) must be supplied. This voltage is only needed for programming, but the nonvolatile registers and EEPROM locations cannot be programmed without it. In order to successfully complete a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set and either the WP pin or the WPEN bit must be LOW. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the STOP condition. BYTE WRITE For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a STOP condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. PAGE WRITE The device is capable of a page write operation. See Figure 14. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. See Figure 15. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a STOP condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. STOP AND WRITE MODES STOP conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a STOP is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. ACKNOWLEDGE POLLING The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the STOP condition is issued to indicate the end of the SA6SA7 SA5 SA3 SA2 SA1 SA0 DEVICE TYPE IDENTIFIER READ / SA4 R/W101 0 WRITEADDRESS EXTERNAL DEVICE Memory Select A1 A0 MS INTERNAL ADDRESS (SA1) INTERNALLY ADDRESSED DEVICE 0E E P R O M A r r a y

1 Control Register,

1 READ

FIGURE 13. SLAVE ADDRESS FORMAT

the host can then proceed with the read or write operation. FIGURE 14. PAGE WRITE OPERATION

5 Bytes

7 Bytes

FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10 FIGURE 16. RANDOM ADDRESS READ SEQUENCE FIGURE 17. CURRENT ADDRESS READ SEQUENCE

acknowledge, and data transfer sequence. requiring a read or write operation for initialization. acknowledge, and data transfer sequence.

• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
• SDA pin is the input mode. Data Protection The following circuitry has been included to prevent inadvertent writes:
• The WEL bit must be set to allow write operations.
• The proper clock count and bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle.
• The WP pin, when held HIGH, prevents all writes to the array and all the Register.
• A programming voltage must be applied to the VP pin prior to any programming sequence. ACK Returned? Issue Slave Address Byte (Read or Write) Byte Load Completed by Issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO Continue Normal Read or Write Command Sequence PROCEED YES

FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8153.0 January 20, 2005 Packaging Information 20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch NOTES: 1. The package outline drawing is compatible with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature SYMBOLS DIMENSIONS IN MILLIMETERS MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 A3 0.19 0.20 0.25 D 4.90 5.00 5.10 D2 3.70 3.80 3.90 E 4.90 5.00 5.10 E2 3.70 3.80 3.90 e — 0.65 — L 0.35 0.40 0.45 y — 0.08 Pin 1 Indent E D A b e L C y C X80140, X80141, X80142, X80143, X80144