X80121Q20I

X80120 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Dual Voltage Monitor and Sequencing - Two independent voltage monitors - Two time delay circuits (in circuit programmable) - Remote delay via SMBus - Programmable voltage thresholds and delay times - Sequence up to 3 power supplies.
• Fault Detection Register - Remote diagnostics of voltage fail event.
• Debounced Manual Reset Input
• Manufacturing/Configuration Memory - 2Kbits of EEPROM - 400kHz SMBus interface
• Available Packages - 20-lead Quad No-Lead Frame (QFN - 5x5mm)

Applications

• General Purpose Timers
• Long Time Delay Generation
• Cycle Timers / Waveform Generation
• ON/OFF Delay Timers
• Supply Sequencing for Distributed Power
• Programmable Delay Event Sequencing
• Multiple DC-DC ON/OFF Sequencing
• Voltage Window Monitoring with Reset
• ON/OFF switches with Programmable Delay
• Voltage Supervisor with Programmable Output Delays
• Databus Power Sequencing
• 100ms to 5 secs Selectable Delay Switches
• ATE or Data Acquisition Timing Applications
• Datapath/Memory Timing Applications
• Data Pipeline Timing Applications
• Batch Timer/Sequencers
• Adjustable Duty Cycle Applications QFN PACKAGE (Top view) V1GDO MR NC DNC DNC V4MON VCC V1MON RESET WPV4GDO SCL 181920 VCC (5mm x 5mm) 91 0 VP DNC SDA VCC VSS

Ordering Information

NUMBER V TRIP1 VTRIP4 PACKAGE X80120Q20I 4.5 0.9 QFN X80121Q20I 3.0 0.9 QFN Data Sheet January 20, 2005

2 FN8151.0 January 20, 2005 Block Diagram MR V1MON V4MON V4GDO V1GDO WP SCL SDA RESET VP EEPROM 2kbits VMON LOGIC VCC BUS INTERFACE VSS VSS VREF1 VREF4 POR CONTROL AND FAULT REGISTERS VSS DIVIDER RESET LOGIC AND DELAY VSS RESET OSC 0.1s 0.5s1s SELECT4 DELAY1 DELAY4 DELAY CIRCUIT REPEATED 2 TIMES X80120, X80121

3 FN8151.0 January 20, 2005 Absolute Maximum Ratings Recommended Operating Conditions V1GDO V V CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications (Standard Settings) Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS VCC Supply Operating Range 4.5 5.5 V ICC Supply Current f SCL = 0kHz 1.0 2.5 mA VP EEPROM programming voltage 9 12 V IP (Note 3) Programming Current 10 mA ILI Input Leakage Current (MR) V IL = GND to VCC 15 µA ILO Output Leakage Current (V1GDO, V4GDO, RESET) 15 µA VIL Input LOW Voltage (MR) -0.5 V CC x 0.3 V VIH Input HIGH Voltage (MR) V CC x 0.7 5.5 V VOL Output LOW Voltage (RESET, V1GDO, V4GDO) IOL = 4.0mA 0.4 V COUT (Note 1) Output Capacitance (RESET, V1GDO, V4GDO) VOUT = 0V 8 pF VTRIP1 V1MON Trip Point Voltage (Range) 2.20 4.70 V X80120 4.45 4.50 4.55 V X80121 2.95 3.00 3.05 V VTRIP4 V4MON Trip Point Voltage 0.85 3.5 V All Versions 0.85 0.90 0.95 V VREF (Note 1) Voltage Reference Long Term Drift 10 years 0 -100 mV AC CHARACTERISTICS tMR (Note 3) Minimum time high for reset valid on the MR pin 5 µs tMRE (Note 3) Delay from MR enable to V1GDO LOW 1.6 µs tDPOR (Note 3) Internal Device Delay on Power up 45 50 55 ms tTO (Note 3) ViGDO turn off time 50 ns X80120, X80121

Electrical Specifications (Programmable Parameters) Over the recommended operating conditions unless otherwise specified. FIGURE 1. INITIAL POWER UP TIMING

1. This parameter is based on characterization data.
2. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

1. This parameter is not 100% tested.

FIGURE 4. BUS TIMING

• It prevents the processor from operating prior to stabilization of the oscillator.
• It allows time for an FPGA to download its configuration prior to initialization of the circuit.
• It prevents communicat ion to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior to system initialization. The POR/RESET circuit is activated when all voltages are within specified ranges and the V1GDO and V4GDO time- out conditions are met. The POR/RESET circuit will then wait t SPOR and de-assert the RESET pin. The POR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100ms, 500ms, 1 second, or 5 seconds. Pin Descriptions PIN NAME DESCRIPTION 1V 4 G D O V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4 and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin. 2 V4MON V4 Voltage Monitor Input. Second voltage monitor pin. If unused connect to V CC.

3 DNC Do Not Connect

6V P EEPROM programming Voltage. The A0 and A1 bits allow for up to 4 X80120 devices to be used on the same SMBus serial interface. buffer is always active (not gated). 11 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 12 V1MON V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC. and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin. the power sequencing is complete. This pin will be released after a programmable delay. 18 NC No Connect. No internal connections. X80120 devices to be used on the same SMBus serial interface. TABLE 1. POR RESET DELAY OPTIONS

system in the event of an abnormal operating condition. released after their programmed delay periods. back to all “1” in preparation for future failure conditions.

1. Power Up of Supplies In Parallel Using Programmable

Delays. (See Figure 7 and Figure 8). failure can be viewed in the Fault Detection Register.

1. Power Up of Supplies Via Relay Sequencing Using

Voltage Monitors (see Figure 9 and Figure 10). TABLE 2. ViGDO OUTPUT TIME DELAY OPTIONS where i is the specific voltage monitor (i = 1, 4). FIGURE 7. EXAMPLE APPLICATION OF PARALLEL POWER

• Control Register (CR)
• Fault Detection Register (FDR)
• EEPROM array Registers The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation.EEPROM Array. The X80120 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Register and Memory Protection In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80120. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin. WEL: Write Enable Latch A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80120. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Note, a write to FDR or RSR does not require that WEL=1. BP1 and BP0: Block Protect Bits The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array. WPEN: Write Protect Enable The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, and CR3) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that are not block protected can be written. Non Volatile Programming Voltage (VP) Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation. BP1 BP0 PROTECTED ADDRESSES (SIZE) ARRAY LOCK 0 0 None (Default) None (Default) 0 1 C0h - FFh (64 bytes) Upper 1/4 1 0 80h - FFh (128 bytes) Upper 1/2 1 1 00h - FFh (256 bytes) All

TABLE 3. WRITE PROTECT CONDITIONS

The device supports a bidirectional bus oriented protocol. master and the device being controlled is called the slave. and then issue a STOP condition. indicating START and STOP conditions (See Figure 11). must be brought LOW prior to the START condition. TABLE 4. REGISTER ADDRESS MAP TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY EEPROM Write Enable WEL CR0 7 WEL = 1 enables write operations to the control registers and EEPROM. WEL = 0 prevents write operations. CR1 4:3 BP1=0, BP0=0 : No EEPROM memory protected. BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected. 1st Voltage Monitor V1OS FDR 0 V1OS = 0 : V1GDO pin has been asserted (must be preset to 1). 4th Voltage Monitor V4OS FDR 3 V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).

immediately after the STOP condition. from the master. The SDA output is at high impedance. write. The contents of the array will not be effected. used to take advantage of the typical 5ms write cycle time.

0 EEPROM Array

1 Control Register,

1 READ

FIGURE 13. SLAVE ADDRESS FORMAT

FIGURE 14. PAGE WRITE OPERATION

5 Bytes

7 Bytes

FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10 FIGURE 16. RANDOM ADDRESS READ SEQUENCE FIGURE 17. CURRENT ADDRESS READ SEQUENCE

acknowledge, and data transfer sequence). requiring a read or write operation for initialization. acknowledge, and data transfer sequence).

• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
• SDA pin is the input mode. Data Protection The following circuitry has been included to prevent inadvertent writes:
• The WEL bit must be set to allow write operations.
• The proper clock count and bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle.
• The WP pin, when held HIGH, prevents all writes to the array and all the Register.
• A programming voltage must be applied to the VP pin prior to any programming sequence. ACK Returned? Issue Slave Address Byte (Read or Write) Byte Load Completed by Issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO Continue Normal Read or Write Command Sequence PROCEED YES

FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8151.0 January 20, 2005 Packaging Information 20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch Note: 1. The package outline drawing is compati- ble with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature SYMBOLS DIMENSIONS IN MILLIMETERS MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 A3 0.19 0.20 0.25 D 4.90 5.00 5.10 D2 3.70 3.80 3.90 E 4.90 5.00 5.10 E2 3.70 3.80 3.90 e — 0.65 — L 0.35 0.40 0.45 y — 0.08 Pin 1 Indent E D A b e L C y C X80120, X80121