X80010 INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 25
Technical content
Features
- Integrates Three Major Functions - Power Sequencing - Hot Swap Controller - System Management Functions
- Penta-Power Sequencing - Sequence up to 5 DC/DC converters. - Four independent voltage enable pins - Four time delay circuits - Soft Power Sequencing - MRC pin restarts sequence without power cycling.
- Hot Swap Controller - Programmable overvoltage and undervoltage protection - Undervoltage lockout for battery/redundant supplies - Electronic circuit breaker - Overcurrent Detection and Gate Shut-off - Overcurrent limit during Insertion - Hardshort retry with retry failure flag - Selectable gate current using IGQ pins (10, 70, 150µA) - MRH pin controls board insertion/extraction. - Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components)
- System Management - Reset output, with delay, holds off host until all supplies are good - Host control of reinsertion with MRH input - Host control of resequencing using MRC input
- Available packages - 32-lead Quad No-Lead Frame (QFN)
Applications
- -48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP
- Card Insertion Detection
- Power Sequencing DC/DC/Power Bricks
- IP Phone Applications
- Databus Power Interfacing
- Custom Industrial Power Backplanes
- Distributed Power Systems Data Sheet January 13, 2005
2 FN8149.0 January 13, 2005 Pinout Typical Application V1GOOD MRCNA1 V3GOOD V2GOOD EN4 EN3 EN1 RESET NA1V4GOOD DRAIN PWRGDSENSE VUV/OV IGQ0VEE GATE VDD FAR BATT-ON MRH IGQ1 NA2 91 0 1 112 13 14 2426272829303132 NA2EN2 81 7 NA1 VEE 25VRGO NA1 NC NC QFN package (Top view) (7mm x 7mm)
Ordering Information
(V) UV1 (V) UV2 (V) tNF (us) VOC (mV) VOCI (mV) OVER CURRENT RETRY RETRY DELAY (ms) IGATE (µA) TDELAY (ms) tPOR (ms) TEMP RANGE (°C) PART MARK X80010Q32I 74.9 42.4 33.2 5 50 150 Always 100 50 100 100 -40 to 85 80010I X80011Q32I 68.0 42.4 33.2 5 50 150 Always 100 50 100 100 -40 to 85 80011I X80012Q32I 74.9 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80012I X80013Q32I 68.0 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80013I VDD X80010, X80011, VUV/OV VEE SENSE DRAIN -48V UV=37V OV=71V -48V GATE Rs 0.02Ω 182k 30k 10k IRFR120 RTN V1GOOD V2GOOD V3GOOD DC/DC Module ON /OFF DC/DC Module ON /OFF DC/DC Module ON /OFF DC/DC Module ON /OFF PWRGD EN1 EN2 EN3 4.7V12V V41000.1uF Back- Plane 100K 4.7K 3.3n X80012, X80013 X80010, X80011, X80012, X80013
3 FN8149.0 January 13, 2005 Absolute Maximum Ratings Recommended Operating Conditions Voltage on given pin (Hot Side Functions): V Voltage on given pin (Cold Side Functions): ENi Supply Voltage (V CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications (Standard Settings) Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS VDD Supply Operating Range 10 12 14 V IDD Supply Current 2.5 5 mA VRGO Regulated 5V output I RGO = 10µA 4.5 6.0 IRGO VRGO current output 50 µA IGATE Gate Pin Current Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) 46.2 52.5 58.8 µA VGATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) 9m A VGATE External Gate Drive (Slew Rate Control) I GATE = 50µA V DD-1 V DD V VPGA Power Good Threshold (PWRGD High to Low) Referenced to VEE VUV1 < VUV/OV < VOV 0.9 1 1.1 V VIHB Voltage Input High (BATT_ON) V EE + 4 V EE + 5 V VILB Voltage Input Low (BATT_ON) VEE + 2 V ILI Input Leakage Current (MRH, MRC) V IL = GND to VCC 10 µA ILO Output Leakage Current (V1GOOD, V2GOOD, V3GOOD, V4GOOD, RESET) All ENi = VRGO for i = 1 to 4 10 µA VIL(3) Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) -0.5 + V EE (VEE + 5) x 0.3 V VIH(3) Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1) (V EE + 5) x 0.7 (VEE + 5) + 0.5 V X80010, X80011, X80012, X80013
4 FN8149.0 January 13, 2005 VOL Output LOW Voltage (RESET, RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR, PWRGD) IOL = 4.0mA (VEE + 2.7 to VEE + 5.5V) IOL = 2.0mA (VEE + 2.7 to VEE + 3.6V) VEE + 0.4 V COUT(1) Output Capacitance (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR) VOUT = 0V 8 pF CIN(1) Input Capacitance (MRH, MRC) V IN = 0V 6 pF VOC Over-current threshold V OC = VSENSE - VEE 45 50 55 mV VOCI Over-current threshold (Insertion) V OC = VSENSE - VEE PWRGD = HIGH Initial Power Up condition 135 150 165 mV VOVR Overvoltage threshold (rising) X80010, X80012 X80011, X80013 Referenced to VEE 3.85 3.49 3.90 3.54 3.95 3.59 V VOVH Overvoltage hysteresis Referenced to V EE 12 18 24 mV VUV1H Undervoltage 1 hysteresis Referenced to V EE BATT-ON = VEE 12 18 24 mV VUV1F Undervoltage 1 threshold (falling) 2.16 2.21 2.26 V VUV2H Undervoltage 2 hysteresis Referenced to V EE BATT-ON = VRGO 12 18 24 mV VUV2F Undervoltage 2 threshold (falling) 1.68 1.73 1.78 V VDRAINF Drain sense voltage threshold (falling) Referenced to VEE 0.9 1 1.1 V VDRAINR Drain sense voltage threshold (rising) Referenced to VEE 1.2 1.3 1.4 V VTRIP1 EN1 Trip Point Voltage Referenced to V EE 2.25 2.5 2.75 V VTRIP2 EN2 Trip Point Voltage Referenced to V EE 2.25 2.5 2.75 V VTRIP3 EN3 Trip Point Voltage Referenced to V EE 2.25 2.5 2.75 V VTRIP4 EN4 Trip Point Voltage Referenced to V EE 2.25 2.5 2.75 V AC CHARACTERISTICS tFOC Sense High to Gate Low 1.5 2.5 3.5 µs tFUV Under Voltage conditions to Gate Low 0.5 1.0 1.5 µs tFOV Overvoltage Conditions to Gate Low 1.0 1.5 2 µs tVFR Overvoltage/undervoltage failure recovery time to Gate =1V. VDD does not drop below 3V, No other failure conditions. 1.2 1.6 2 µs tBATT_ON Delay BATT_ON Valid 100 ns tMRC Minimum time high for reset valid on the MRC pin 5 µs tMRH Minimum time high for reset valid on the MRH pin 5 µs tMRCE Delay from MRC enable to PWRGD HIGH No Load 1.0 1.6 µs tMRCD Delay from MRC disable to PWRGD LOW Gate is On, No Load 200 400 µs tMRHE Delay from MRH enable to Gate Pin LOW I GATE = 60µA, No Load 1.0 1.6 2.4 µs tMRHD Delay from MRH disable to GATE reaching 1V I GATE = 60µA, No Load 1.8 2.6 µs Electrical Specifications (Standard Settings) Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT X80010, X80011, X80012, X80013
5 FN8149.0 January 13, 2005 Equivalent A.C. Output Load Circuit tRESET_E Delay from PWRGD or ViGOOD to RESET valid LOW 1 µs tQC Delay from IGQ1 and IGQ0 to valid Gate pin current 1 µs tSC_RETRY Delay between Retries 85 100 115 ms tNF Noise Filter for Overcurrent 4.5 5 5.5 µs tDPOR Device Delay before Gate assertion 45 50 55 ms tSPOR Delay after PWRGD and all ViGOOD signals are active before RESET assertion 85 100 115 ms tDELAY1 Power Sequencing Time Delay TiD1 = 0; TiD0 = 0 85 100 115 ms tDELAY2 tDELAY3 tDELAY4 tTO ViGOOD turn off time 50 ns tPDHLPG(1) Delay from Drain good to PWRGD LOW Gate = V DD 1 µs tPDLHPG(1) Delay from Drain fail to PWRGD HIGH Gate = V DD 1 µs tPGHLPG(1) Delay from Gate good to PWRGD LOW Drain = V EE 1 µs tPGLHPG(1) Delay from Gate fail to PWRGD HIGH Drain = V EE 1 µs NOTE: 1. This parameter is based on characterization data. Electrical Specifications (Standard Settings) Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load 4.6kΩ RESET 30pF V1GOOD , 4.6kΩ 30pF V2GOOD , V3GOOD , V4GOOD FAR PWRGD X80010, X80011, X80012, X80013
FIGURE 29. BLOCK DIAGRAM
13 FN8149.0 January 13, 2005 Pin Configuration V1GOOD MRCNA1 V3GOOD V2GOOD EN4 EN3 EN1 RESET NA1V4GOOD DRAIN PWRGDSENSE VUV/OV IGQ0VEE GATE VDD FAR BATT-ON MRH IGQ1 NA2 91 0 1 1 12 13 14 26272829303132 X80010, X80011, X80012, X80013 32-lead QFN Quad Package NA2EN2 81 7 NA1 VEE VRGO NA1 NC NC (7mm x 7mm) Pin Descriptions PIN NAME DESCRIPTION 1V RGO Regulated 5V output. Used to pull-up user programmable inputs IGQ0, IGQ1, BATT-ON (if needed). 2N A 1 Not Available. Do not connect to this pin. 3 V4GOOD V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than VTRIP4 and goes HIGH when EN4 is greater than VTRIP4. There is a user selectable delay circuitry on this pin. 4E N 4 V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to VRGO. 5 V3GOOD V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than VTRIP3 and goes HIGH when EN3 is greater than VTRIP3. There is a user selectable delay circuitry on this pin. 6E N 3 V3 Voltage Enable Input. Third voltage enable pin. If unused connect to VRGO. 7 V2GOOD V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than VTRIP2 and goes HIGH when EN2 is greater than VTRIP2. There is a user selectable delay circuitry on this pin. 8E N 2 V2 Voltage Enable Input. Second voltage enable pin. If unused connect to VRGO. 9V DD Positive Supply Voltage Input. 10 V EE Negative Supply Voltage Input. 11 V UV/OV Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or overvoltage condition. 12 SENSE Circuit Breaker Sense Input. This input pin detects the overcurrent condition. 13 GATE Gate Drive Output. Gate drive output for the external N-channel MOSFET. 14 DRAIN Drain. Drain sense input of the external N-channel MOSFET. 15 NA1 Not Available. Do not connect to this pin. 16 NA1 Not Available. Do not connect to this pin. 17 NA2 Not Available. Connect to VRGO. 18 NA2 Not Available. Connect to VRGO. 19 EN1 V1 Voltage Enable Input. First voltage enable pin. If unused connect to VRGO. 20 V1GOOD V1 Voltage Good Output (Active Low).This open drain output goes LOW when EN1 is less than VTRIP1 and goes HIGH when EN1 is greater than VTRIP1. There is a user selectable delay circuitry on this pin. X80010, X80011, X80012, X80013
- Noise filtering of the current monitor input.
- Relaxed over-current limits for initial board insertion.
- Over-current recove ry retry operation.
the board into the backplane large currents may be induced. overcurrent setting during insertion. threshold voltage during insertion is 150mV. to monitor for over-current conditions. off and all power good indicators go inactive. FIGURE 35. OVERCURRENT DETECTION/SHORT CIRCUIT
voltage from rising and keep the FET from turning on. the gate low. Use the following formula for choosing C1. prevent high frequency oscillations. on this pin is less than VEE - 1V, then a fault condition exists. used, provides several benefits. operate with insufficient voltage. stabilization of the oscillator. prior to initialization of the circuit. FIGURE 38. DRAIN SENSE AND POWER GOOD INDICATOR
on the selected gate control mechanism. sequencing schemes for downstream DC/DC supplies. Below are examples of parallel and relay sequencing.
- Power Up of DC/DC Supplies In Parallel Sequencing
be increased with the use of external R-C circuits. TABLE 3. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL)
1 Operational When MRH is HIGH the Manual Reset
TABLE 4. MANUAL RESET OF THE COLD SIDE (PWRGD
1 HIGH MRC must be held HIGH minimum of 5 µs
0 Operational When MRC is LOW the MRC
5 FPGA
5 ASIC
FIGURE 41. TYPICAL APPLICATION OF HOTSWA P AND DC/DC PARALLEL POWER SEQUENCING
- Power Up of DC/DC Supplies Via Relay Sequencing
preceding DC/DC supply voltage output is valid. FIGURE 42. PARALLEL SEQUENCING OF DC/DC SUPPLIES.
FIGURE 43. TYPICAL APPLICATION OF HOTSWAP AND DC/DC RELAY SEQUENCING
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. FIGURE 44. RELAY SEQUENCING OF DC/DC SUPPLIES. (TIMING)
25 FN8149.0 January 13, 2005 Packaging Information 0.009 (0.23) 0.015 (0.38) 0.185 (4.70) 0.271 (6.90) 0.279 (7.10) 0.014 (0.35) 0.029 (0.75) (4.70) 0.185 (4.70) 0.027 (0.70) 0.031 (0.80) 0.000 (0.00) 0.030 (0.76) 0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05) 0.271 (6.90) 0.279 (7.10) 0.271 (6.90) 0.279 (7.10) PIN 1 INDENT 32-Lead Very Very Thin Quad Flat No Lead Package 7mm x 7mm Body with 0.65mm Lead Pitch X80010, X80011, X80012, X80013