X80000Q32I

X80000 INTERSIL | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 37

Technical content

Features

Integrates Three Major Functions - Smart Power Plug communications - Programmable power sequencing - Programmable Hot Swap controller
Smart Power Plug™ - Intelligent board insertion allows verification of board and power supply resources prior to system insertion. - Fault detection register records the cause of the faults - Soft extraction - Soft re-insertion - Remote gate shutdown/turn on - Power ID/manufacturing ID memory (2kb of EEPROM)
Programmable Power Sequencing - Sequence up to 5 DC/DC converters. - Four independent voltage enable pins - Four programmable time delay circuits - Soft Power Sequencing - restart sequence without power cycling.
Hot Swap Controller - Programmable overvoltage and undervoltage protection - Undervoltage lockout for battery/redundant supplies - Programmable slew rate for external FET gate control - Electronic circuit breaker - overcurrent detection and gate shut-off - Programmable overcurrent limit during Insertion - Programmable hardshort retry with retry failure flag - Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components)
Available Packages - 32-lead Quad No-Lead Frame (QFN)

Applications

-48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP
Card Insertion Detection
Power Sequencing DC-DC/Power Bricks
IP Phone Applications
Databus Power Interfacing
Custom Industrial Power Backplanes
Distributed Power Systems Data Sheet March 18, 2005

2 FN8148.0 March 18, 2005 Pinout X80000, X80001 (7X7 QFN) TOP VIEW Typical Application V1GOOD MRCA0 V3GOOD V2GOOD EN4 EN3 EN1 RESET WPV4GOOD DRAIN PWRGDSENSE VUV/OV IGQ0VEE GATE VDD FAR BATT-ON MRH IGQ1 SCL 91 0 1 1 12 13 14 26272829303132 SDAEN2 81 7 NC VEE VRGO NC NC (7mm x 7mm)

Ordering Information

X80000Q32I 74.9 42.4 33.2 I 32 Ld QFN 80000I X80001Q32I 68.0 42.4 33.2 I 32 Ld QFN 80001I VDD X80000 VUV/OV VEE SENSE DRAIN -48V UV=37V OV=71V -48V GATE Rs 0.02Ω 182K 30K 10K IRFR120 RTN 100K V1GOOD V2GOOD V3GOOD DC-DC Module ON /OFF DC-DC Module ON /OFF DC-DC Module ON /OFF DC-DC Module ON /OFF PWRGD EN1 EN2 EN3 SCLSCL 4.7V12V X80001 V41000.1µF SDA Back- Plane SDA MRH Opto- IsolationInsert Control 4.7K 3.3n X80000, X80001

3 FN8148.0 March 18, 2005 Absolute Maximum Ratings Recommended Operating Conditions Voltage on given pin (Hot Side Functions): Voltage on given pin (Cold Side Functions): Supply Voltage (V CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications Standard Settings Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS VDD Supply Operating Range 10 12 14 V IDD Supply Current 2.5 5 mA VRGO Regulated 5V output I RGO = 10µA 4.5 5.5 IRGO VRGO current output 50 µA IGATE Gate Pin Current Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) 46.2 52.5 58.8 µA VGATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) 9m A VGATE External Gate Drive (Slew Rate Control) I GATE = 50µA V DD-0.01 V DD V VPGA Power Good Threshold (PWRGD High to Low) Referenced to V EE VUV1 < VUV/OV < VOV 0.9 1 1.1 V VIHB Voltage Input High (BATT_ON) V EE + 4 V EE + 5 V VILB Voltage Input Low (BATT_ON) VEE + 2 V ILI Input Leakage Current (MRH, MRC) V IL = GND to VCC 10 µA ILO Output Leakage Current (V1GOOD, V2GOOD, V3GOOD, V4GOOD, RESET) All ENi = VRGO for i = 1 to 4 10 µA VIL Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) -0.5 + VEE (VEE + 5) x 0.3 V VIH Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1) (V EE + 5) x 0.7 (VEE + 5) + 0.5 V X80000, X80001

4 FN8148.0 March 18, 2005 VOL Output LOW Voltage (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR, PWRGD) IOL = 4.0mA V EE + 0.4 V COUT (Note 1) Output Capacitance (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR) VOUT = 0V 8 pF CIN (Note 1) Input Capacitance (MRH , MRC) V IN = 0V 6 pF VOC Overcurrent threshold V OC = VSENSE - VEE 45 50 55 mV VOCI Overcurrent threshold (Insertion) V OC = VSENSE - VEE PWRGD = HIGH Initial Power Up condition 135 150 165 mV VOVR Overvoltage threshold (rising) X80000 Referenced to V EE 3.85 3.90 3.95 V X80001 3.49 3.54 3.59 V VOVF Overvoltage threshold (falling) X80000 Referenced to V EE 3.82 3.87 3.92 V X80001 3.46 3.51 3.56 V VUV1R Undervoltage 1 threshold (rising) Referenced to V EE BATT-ON = VEE 2.19 2.24 2.29 V VUV1F Undervoltage 1 threshold (falling) 2.16 2.21 2.26 V VUV2R Undervoltage 2 threshold (rising) Referenced to V EE BATT-ON = VRGO 1.71 1.76 1.81 V VUV2F Undervoltage 2 threshold (falling) 1.68 1.73 1.78 V VDRAINF Drain sense voltage threshold (falling) Referenced to V EE 0.9 1 1.1 V VDRAINR Drain sense voltage threshold (rising) Referenced to V EE 1.2 1.3 1.4 V VTRIP1 (Note 1) EN1 Trip Point Voltage Referenced to V EE VRGO ÷ 2 V VTRIP2 (Note 1) EN2 Trip Point Voltage Referenced to V EE V VTRIP3 (Note 1) EN3 Trip Point Voltage Referenced to V EE V VTRIP4 (Note 1) EN4 Trip Point Voltage Referenced to V EE V AC CHARACTERISTICS tFOC Sense High to Gate Low 1.5 2.5 3.5 µs tFUV Under Voltage conditions to Gate Low 0.5 1 1.5 µs tFOV Overvoltage Conditions to Gate Low 1.0 1.5 2 µs tVFR Overvoltage/undervoltage failure recovery time to Gate =1V. VDD does not drop below 3V, No other failure conditions. 1.2 1.6 2 µs tBATT_ON Delay BATT_ON Valid 100 ns tMRC Minimum time high for reset valid on the MRC pin 5 µs tMRH Minimum time high for reset valid on the MRH pin 5 µs tMRCE Delay from MRC enable to PWRGD HIGH No Load 1.0 1.6 µs tMRCD Delay from MRC disable to PWRGD LOW Gate is On, No Load 200 400 ns tMRHE Delay from MRH enable to Gate Pin LOW I GATE = 60µA, No Load 1.0 1.6 2.4 µs Electrical Specifications Standard Settings Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT X80000, X80001

5 FN8148.0 March 18, 2005 Equivalent A.C. Output Load Circuit tMRHD Delay from MRH disable to GATE reaching 1V I GATE = 60µA, No Load 1.8 2.6 µs tRESET_E Delay from PWRGD or ViGOOD to RESET valid LOW 1 µs tQC Delay from IGQ1 and IGQ0 to valid Gate pin current 1 µs tSC_RETRY Delay between retries TSC1 = 0; TSC0 = 0 90 100 110 ms tNF Noise Filter for Overcurrent TF1 = 0; TF0 = 1 4.5 5 5.5 µs tDPOR Device Delay before Gate assertion 45 50 55 ms tSPOR Delay after PWRGD and all ViGOOD signals are active before RESET assertion TPOR1 = 0; TPOR0 = 0 90 100 110 ms tTO ViGOOD turn off time 50 ns tPDHLPG (Note 1) Delay from Drain good to PWRGD LOW Gate = V DD 1 µs tPDLHPG (Note 1) Delay from Drain fail to PWRGD HIGH Gate = V DD 1 µs tPGHLPG (Note 1) Delay from Gate good to PWRGD LOW Drain = V EE 1 µs tPGLHPG (Note 1) Delay from Gate fail to PWRGD HIGH Drain = V EE 1 µs NOTE: 1. This parameter is based on characterization data. Electrical Specifications Standard Settings Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load SDA 30pF 4.6kΩ RESET 30pF V1GOOD , 4.6kΩ 30pF V2GOOD , V3GOOD , V4GOOD , FAR 4.6kΩ PWRGD X80000, X80001

8 FN8148.0 March 18, 2005 Electrical Specifications Programmable Parameters Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT DC CHARACTERISTICS VCB Over Current Trip Voltage Range Factory Setting is 50mV (see VOCI). 30 100 mV IGATE (VCB = VSENSE - VEE) For other options, contact Intersil. -12 12 % Gate Pin Pull-Up Current. (error) (current) Gate Drive On; VGATE = VEE, IGQ1=0; IGQ0=0 IG3 = 0; IG2= 0; IG1 = 0; IG0 = 0 Factory Default 9.2 10.5 11.8 µA IG3 = 0; IG2= 0; IG1 = 0; IG0 = 1 21.0 µA IG3 = 0; IG2= 0; IG1 = 1; IG0 = 0 31.5 µA IG3 = 0; IG2= 0; IG1 = 1; IG0 = 1 42.0 µA IG3 = 0; IG2= 1; IG1 = 0; IG0 = 0 46.2 52.5 58.5 µA IG3 = 0; IG2= 1; IG1 = 0; IG0 = 1 63.0 µA IG3 = 0; IG2= 1; IG1 = 1; IG0 = 0 64.7 73.5 82.3 µA IG3 = 0; IG2= 1; IG1 = 1; IG0 = 1 84.0 µA IG3 = 1; IG2= 0; IG1 = 0; IG0 = 0 94.5 µA IG3 = 1; IG2= 0; IG1 = 0; IG0 = 1 105.0 µA IG3 = 1; IG2= 0; IG1 = 1; IG0 = 0 115.5 µA IG3 = 1; IG2= 0; IG1 = 1; IG0 = 1 126.0 µA IG3 = 1; IG2= 1; IG1 = 0; IG0 = 0 136.5 µA IG3 = 1; IG2= 1; IG1 = 0; IG0 = 1 147.0 µA IG3 = 1; IG2= 1; IG1 = 1; IG0 = 0 138.6 157.5 176.4 µA IG3 = 1; IG2= 1; IG1 = 1; IG0 = 1 168.0 µA IG3-IG0 = Don’t Care IGQ1=0; IGQ0=1 9.2 10.57 11.8 µA IG3-IG0 = Don’t Care IGQ1=1; IGQ0=0 64.7 73.5 82.3 µA IG3-IG0 = Don’t Care IGQ1=1; IGQ0=1 138.6 157.5 176.4 µA V PGA Power Good Threshold Accuracy V DRAIN - VEE, High to Low Transition. Default Factory Setting is 47V. ±400 mV VOCI Over current threshold (Insertion) Referenced to VEE VS1 = 0 VS0 = 0 PWRGD = HIGH 45 50 55 mV VS1 = 0 VS0 = 1 Factory Default 90 100 110 mV VS1 = 1 VS0 = 0 135 150 165 mV VS1 = 1 VS0 = 1 180 200 220 mV AC CHARACTERISTICS t SC_RETRY Delay between Retries Factory Default TSC1 = 0 TSC0 = 0 90 100 110 ms TSC1 = 0 TSC0 = 1 450 500 550 ms TSC1 = 1 TSC0 = 0 0.9 1 1.1 s TSC1 = 1 TSC0 = 1 4.5 5 5.5 s X80000, X80001

9 FN8148.0 March 18, 2005 tNF Noise Filter for Overcurrents Factory Default F1 = 0 F0 = 0 0µ s F1 = 0 F0 = 1 4.5 5 5.5 µs F1 = 1 F0 = 0 9 10 11 µs F1 = 1 F0 = 1 18 20 22 µs t SPOR Delay before RESET assertion Factory Default TPOR1 = 0 TPOR0 = 0 90 100 110 ms TPOR1 = 0 TPOR0 = 1 450 500 550 ms TPOR1 = 1 TPOR0 = 0 0.9 1 1.1 s TPOR1 = 1 TPOR0 = 1 4.5 5 5.5 s t DELAYi Time Delay used in Power Sequencing (i = 1 to 4) Factory Default TiD1 = 0 TiD0 = 0 90 100 110 ms TiD1 = 0 TiD0 = 1 450 500 550 ms TiD1 = 1 TiD0 = 0 0.9 1 1.1 s TiD1 = 1 TiD0 = 1 4.5 5 5.5 s Serial Interface Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS ICC1 (Note 1) Active Supply Current (VDD) Read to Memory or CRs VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz 2.5 mA ICC2 (Note 1) Active Supply Current (VDD) Write to Memory or CRs 3.0 mA ILI Input Leakage Current (SCL, WP , A0, A1) V IL = GND to VCC 10 µA ILO Output Leakage Current (SDA) V SDA = GND to VCC Device is in Standby (Note 2) 10 µA VIL (Note 3) Input LOW Voltage (SDA, SCL, WP, A0, A1) -0.5 + VEE (V EE + 5) x 0.3 V VIH (Note 3) Input HIGH Voltage (SDA, SCL, WP , A0, A1) (V EE + 5) x 0.7 (VEE + 5) + 0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed input level V EE + 0.2 V VCC related level .05 x (VEE + 5) V VOL Output LOW Voltage (SDA) I OL = 4.0mA (2.7-5.5V) IOL = 2.0mA (2.4-3.6V) VEE + 0.4 V AC CHARACTERISTICS fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 1.5 µs Electrical Specifications Programmable Parameters Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT X80000, X80001

t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Over the recommended operating conditions unless otherwise specified. FIGURE 7. BUS TIMING

FIGURE 21. BLOCK DIAGRAM

15 FN8148.0 March 18, 2005 Pin Configuration V1GOOD MRCA0 V3GOOD V2GOOD EN4 EN3 EN1 RESET WPV4GOOD DRAIN PWRGDSENSE VUV/OV IGQ0VEE GATE VDD FAR BATT-ON MRH IGQ1 SCL 91 0 1 1 12 13 14 26272829303132 X80000/X80001 32-lead QFN Quad Package SDAEN2 81 7 NA VEE VRGO NC NC (7mm x 7mm) Pin Descriptions PIN NAME DESCRIPTION 1V RGO Regulated 5V output. Used to pull-up user programmable inputs IGQ0, IGQ1, BATT-ON, A1, A0, and WP (if needed). 2A 0 Address Select Input. It has an internal pulldown resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface. 3 V4GOOD V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than VTRIP4 and goes HIGH when EN4 is greater than VTRIP4. There is a user selectable delay circuitry on this pin. 4E N 4 V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to VRGO. 5 V3GOOD V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than VTRIP3 and goes HIGH when EN3 is greater than VTRIP3. There is a user selectable delay circuitry on this pin. 6E N 3 V3 Voltage Enable Input. Third voltage enable pin. If unused connect to VRGO. 7 V2GOOD V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than VTRIP2 and goes HIGH when EN2 is greater than VTRIP2. There is a user selectable delay circuitry on this pin. 8E N 2 V2 Voltage Enable Input. Second voltage enable pin. If unused connect to VRGO. 9V DD Positive Supply Voltage Input. 10 V EE Negative Supply Voltage Input. 11 V UV/OV Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or overvoltage condition. 12 SENSE Circuit Breaker Sense Input. This input pin detects the overcurrent condition. 13 GATE Gate Drive Output. Gate drive output for the external N-channel MOSFET. 14 DRAIN Drain. Drain sense input of the external N-channel MOSFET. 15 NA Not Available. Do not connect to this pin. 16 A1 Address Select Input. It has an internal pulldown resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4 X80000 devices to be used on the same SMBus serial interface. 17 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 18 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 19 EN1 V1 Voltage Enable Input. First voltage enable pin. If unused connect to VRGO. X80000, X80001

system) then cleared by a write to Fault Detection Register. Please refer to FDR section. See Table 2.

Overcurrent shut-down of the power FET and external power good indicators.
Noise filtering of the current monitor input.
Relaxed overcurrent limits for initial board insertion.
Overcurrent recovery retry operation.
Flag of overcurrent fault condition.
Flag of overcurrent retry failure. A sense resistor, placed in the supply path between V EE and SENSE (see Figure 22) generates a voltage internal to the X80000. When this voltage exceeds 50mV, an over current condition exists and an internal “circuit breaker” trips, turning off the gate drive to the external FET. The actual overcurrent level is dependent on the value of the current sense resistor. For example a 20mΩ sense resistor sets the overcurrent level to 2.5A. Intersil’s X80000 provides a safety mechanism during insertion of the board into the back plane. During insertion of the board into the backplane large currents may be induced. In order to prevent premature shut down of the external FET, the X80000 allows for a choice of up to 4 times the overcurrent setting during insertion. After the PWRGD signal is asserted, the X80000 switches back to the normal overcurrent setting. The overcurrent threshold voltage during insertion can be changed from 50mV to 100mV, 150mV, or 200mV, by setting bits in Control Register CR4. After the Power FET turns off due to an overcurrent condition, a retry circuit turns the FET back on after a delay of t SC_RETRY. If the overcurrent condition remains, the FET again turns off. This sequence repeats until the overcurrent condition is released. There are various other options that program the retry circuit to change the number of retries or to not retry. An optional output signal, FAR , indicates a failure after retry. Overcurrent Shut-down As shown in Figure 27, this circuit block contains a resistor ladder, a comparator, a noise filter and a programmable voltage reference to monitor for overcurrent conditions. The overcurrent voltage threshold (V OC) is 50mV. This can be factory set, by special order, to any setting between 30mV and 100mV. VOC is the voltage between the SENSE and VEE pins and across the RSENSE resistor. If the selected sense resistor is 20mΩ, then 50mV corresponds to an overcurrent of 2.5A. If an overcurrent condition is detected, the GATE is turned off, all power good indicators go inactive and an overcurrent failure bit (FOC) is set. Overcurrent Noise Filter The X80000 has a noise (low pass) filter built into the overcurrent comparator. The comparator will thus ignore current spikes shorter than 5µs. Other filter options are provided by setting control bits in register CR4. The control bits set the comparator to ignore current spikes shorter that 5µs, 10µs or 20µs and allow the filter to be turned off.

TABLE 3. OVERVOLTAGE/UNDERVOLTAGE FLAG BITS FIGURE 26. PROGRAMMABLE UNDERVOLTAGE AND TABLE 4. NOISE FILTER FOR OVER CURRENTS

located in the CR2 register.

Master Reset Hot Side. The master reset pin, MRH, can

default values are restored and the retry is cleared.

Power cycle the part, turning V DD OFF, then ON.

gate pin will proceed to open at the user defined slew rate. TABLE 5. INSERTION OVERCURRENT THRESHOLD OPTIONS FIGURE 27. OVERCURRENT DETECTION/SHORT CIRCUIT PROTECTION WITH PROGRAMMBLE RETRY AND FLAG MONITORS

instructions on writing to the FDR (See Table 9). overvoltage conditions exist. GATE current using four IGATE control bits. between 10µA to 160µA in 10µA increments. TABLE 6. RETRY AND EVENT SEQUENCE OPTIONS

001 N RETRY = 1 (one retry), assert FAR pin after

010 N RETRY = 2 (two retries), assert FAR pin after

011 N RETRY = 3 (three retries), assert FAR pin after

100 N RETRY = 4 (four retries), assert FAR pin after

101 N RETRY = 5 (five retries), assert FAR pin after

111 N RETRY = 0 (no retry), asset FAR, and shutoff

TABLE 7. RETRY EVENT DELAY OPTIONS TABLE 8. OVERCURRENT FLAG BIT or hardshort retry is initiated. TABLE 9. RETRY COUNT FAILURE STATUS BIT FAR_STAT if FAR_STAT = 1, FAR is asserted. FIGURE 28. SELECTING I GATE CURRENT FOR SLEW RATE

values for C2 range from 2.2 to 4.7nF. voltage from rising and keep the FET from turning on. the gate low. Use the following formula for choosing C1. prevent high frequency oscillations. FIGURE 29. PROGRAMMBLE SLEW RATE (INRUSH TABLE 10. I GATE OUTPUT CURRENT OPTIONS

change in the GATE pin current is less than 1 µsecond. on this pin is less than VEE - 1V, then a fault condition exists.

there is no overvoltage or no undervoltage condition, (i.e. undervoltage < VEE < overvoltage.)
There is no overcurrent condition (i.e. V EE - VSENSE < VOC.)
The FET is turned on (i.e. VDRAIN < VEE + 1V and VGATE > VDD - 1V). Power On Reset and System Reset With Delay Application of power to the X80000 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, provides several benefits.
It prevents the system microprocessor from starting to operate with insufficient voltage.
It prevents the processor from operating prior to stabilization of the oscillator.
It allows time for an FPGA to download its configuration prior to initialization of the circuit.
It prevents communicati on to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up. The SPOR/RESET circuit is activated when all voltages are within specified ranges and the following time-out conditions are met: PWRGD and V1GOOD, V2GOOD, V3GOOD, and V4GOOD. The SPOR/RESET circuit will then wait 100ms and assert the RESET pin. The SPOR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100 ms, 500 ms, 1 second, or 5 seconds. IGQ1 PIN IGQ0 PIN CONTENTS 0 0 Defaults to gate current set by IG3:IG0 bits 0 1 Gate Current is 10 µA 1 0 Gate Current is 70 µA 1 1 Gate Current is 150 µA

TABLE 11. SPOR RESET DELAY OPTIONS FIGURE 30. DRAIN SENSE AND POWER GOOD INDICATOR

preparation for future monitored conditions. (RSR) will shutdown the gate and the gate will be pulled low. sequencing schemes for downstream DC-DC supplies.

Power Up of DC-DC Supplies In Parallel Sequencing
Power Up of DC-DC Supplies Via Relay Sequencing

TABLE 13. MANUAL RESET OF TH E HOT SIDE (GATE SIGNAL)

1 Operational When MRH is HIGH the Manual Reset (Hot)

TABLE 14. MANUAL RESET OF THE COLD SIDE (PWRGD

1 HIGH MRC must be held HIGH minimum of 5 µsecs

0 Operational When MRC is LOW the MRC function is

5 FPGA

5 ASIC

FIGURE 33. TYPICAL APPLICATION OF HOTSWAP AND DC-DC PARALLEL POWER SEQUENCING

FIGURE 34. PARALLEL SEQUENCING OF DC-DC SUPPLIES (TIMING)

FIGURE 35. TYPICAL APPLICATION OF HOTSWAP AND DC-DC RELAY SEQUENCING

Control Register (CR)
Fault Detection Register (FDR)
Remote Shutdown Register (RSR)
EEPROM array Registers The Control Registers, Remote Shutdown Register and Fault Detection Register are summarized in Table 15. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. It is important to remember that, in most cases, the SMBus serial port must be isolated between the X80000, which is referenced to -48V, and the system controller, which is referenced to ground. EN2 In tDELAY1 V1GDO Power Supply #1 turns ON Power Supply V2MON threshold Power Supply #3 turns ON V2GDO 100ms V3GDO Programmable Delay Programmable Delay #1 OUTPUT 500ms 1sec 5sec 100ms 500ms 1sec 5sec tDELAY2 Power Supply #2 turns ON V3MON threshold 100ms 500ms 1sec 5sec tDELAY3 Programmable Delay Power Supply #2 OUTPUT V4MON Power Supply #3 OUTPUT threshold tDELAY4 Programmable Delay V4GDO (from PWRGD ) (3.3V) (2.5V) (1.8V) tRESET Programmable Delay RESET 100ms 500ms 1sec 5sec 100ms 500ms 1sec 5sec FET turns ON Select t DELAYx and tRESET via the 2-wire interface. EN2 EN3 Power Supply #4 OUTPUT (1.2V) EN4 Power Supply #4 turns ON

FIGURE 36. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING)

WEL bit), so they do not change when power is removed. TABLE 15. REGISTER ADDRESS MAP TABLE 16. FAULT DETECTION BITS SUMMARY FAR_STAT FDR 4 Retry Violation FAR_STAT = 0 : Failure After retry detected (must be preset to 1). FOC FDR 5 Overcurrent Violation FOC = 0 : Over current detected (must be preset to 1). FOV FDR 7 Overvoltage Violation FOV = 0 : Over voltage detected (must be preset to 1). FUV1/2 FDR 6 Undervoltage Violation FUV1/2 = 0 : Under voltage detected (must be preset to 1). V1OS FDR 0 1st Voltage Good V1OS = 0 : V1GOOD pin has been asserted (must be preset to 1). V2OS FDR 1 2nd Voltage Good V2OS = 0 : V2GOOD pin has been asserted (must be preset to 1). V3OS FDR 2 3rd Voltage Good V3OS = 0 : V3GOOD pin has been asserted (must be preset to 1). V4OS FDR 3 4th Voltage Good V4OS = 0 : V4GOOD pin has been asserted (must be preset to 1).

TABLE 17. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY CR2 7:4 Gate Current Select See Table 10. CR1 2:0 Retry Sequence Options See Table 6. WEL CR0 7 Write Enable WEL = 1 enables write operat ions to the control registers and EEPROM. WEL = 0 prevents write operations. CR1 4:3 EEPROM Block Protect BP1=0, BP0=0 : No EEPROM memory protected. BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected.

entire contents of the EEPROM memory. Enable bit and a Write Protect pin. only 00h or 80h to the CR0 register. control register) or until the part powers up again. Note, a write to FDR or RSR does not require that WEL=1. not block protected can be written. TABLE 18. WRITE PROTECT CONDITIONS

The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted.
The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers.
The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 39). Serial Write Operations In order to perform a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. Page Write The device is capable of a page write operation (See Figure 40). It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page (See Figure 41). This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Stop and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation (See Figure 44). SA6SA7 SA5 SA3 SA2 SA1 SA0 DEVICE TYPE IDENTIFIER READ / SA4 R/W101 0 WRITEADDRESS EXTERNAL DEVICE Memory Select A1 A0 MS INTERNAL ADDRESS (SA1) INTERNALLY ADDRESSED DEVICE 0E E P R O M A r r a y

1 Control Register,

1 READ

FIGURE 39. SLAVE ADDRESS FORMAT

FIGURE 40. PAGE WRITE OPERATION

5 Bytes

7 Bytes

FIGURE 41. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10 FIGURE 42. RANDOM ADDRESS READ SEQUENCE FIGURE 43. CURRENT ADDRESS READ SEQUENCE

requiring a read or write operation for initialization.

The device is in the low power standby state.
The WEL bit is set to ‘0’. In this state, it is not possible to write to the device.
SDA pin is the input mode. Data Protection The following circuitry has been included to prevent inadvertent writes:
The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ACK Returned? Issue Slave Address Byte (Read or Write) Byte Load Completed by Issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO Continue Normal Read or Write Command Sequence PROCEED YES

FIGURE 44. ACKNOWLEDGE POLLING SEQUENCE

36 FN8148.0 March 18, 2005 Packaging Information 0.009 (0.23) 0.015 (0.38) 0.185 (4.70) 0.025 (0.65) BSC 0.014 (0.35) 0.029 (0.75) (4.70) 0.185 (4.70) 0.027 (0.70) 0.031 (0.80) 0.000 (0.00) 0.030 (0.76) 0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05) 0.271 (6.90) 0.279 (7.10) 0.271 (6.90) 0.279 (7.10) PIN 1 INDENT 32-Lead Very Very Thin Quad Flat No Lead Package 7mm x 7mm Body with 0.65mm Lead Pitch X80000, X80001

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8148.0 March 18, 2005 X80000, X80001

Summary

Smart Power Plug Penta-Power Sequence Controller with Hot Swap March 18, 2005

Description