X68C75PI

X68C75 XICOR | Alldatasheet

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Technical content

X68C75 SLIC® E2 X68C75 SLIC® E2 Microperipheral

FEATURES

• Highly Integrated Microcontroller Peripheral —8K x 8 E2 Memory —2 x 8 General Purpose Bidirectional I/O Ports —16 x 8 General Purpose Registers —Integerated Interrupt Controller Module —Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC) —On-Chip BIOS and Boot Loader —IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write —Dual Plane Architecture
• Isolates Read/Write Functions Between Planes
• Allows Continuous Execution Of Code From One Plane While Writing In The Other Plane
• Multiplexed Address/Data Bus —Direct Interface to Popular 68HC11 Family of Microcontrollers
• Software Data Protection —Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection —Set Write Lockout in 1K Blocks
• Toggle Bit Polling ©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 2899-2.1 4/11/97 T0/C0/D1 SH Port Expander and E2 Memory PIN CONFIGURATIONS
• High Performance CMOS —Fast Access Time, 120ns —Low Power
• 60mA Active
• 100 µA Standby
• PDIP, PLCC, and TQFP Packaging Available

DESCRIPTION

The X68C75 is a highly integrated peripheral for the 68HC11 family of microcontrollers. The device inte- grates 8K-bytes of 5V byte-alterable nonvolatile memory, 2 bidirectional 8-bit ports, 16 general purpose registers, programmable internal address decoding and a multi- plexed address and data bus. The 5V byte-alterable nonvolatile memory can be used as program storage, data storage, or a combination of both. The memory array is separated into two 4K-byte sections which allows read accesses to one section while a write operation is taking place in the other section. The nonvolatile memory also features Software Data Protection to protect the contents during power transitions, and an advanced Block Protect register which allows individual blocks of the memory to be configured as read-only or read/write.

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E A10 CE A/D7 A/D6 A/D5 X68C75 DIP SLIC Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc. A PPLICA TION NOTES A V AILABLE AN62 • AN64 • AN66 • AN74 INDEX CORNER 2899 ILL F02.3 6 5 4 3 2 1 44 43 42 41 40 18 19 20 22 23 24 25 26 27 2821 A15 STRASEL WC A12 RESET VCC R/WAS A8 A9 A11 IRQ STRB PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 A14 A13 PA 7 PA 6 PA 5 PA 4 PA 333 PA 2 PA 1 PA 0 A/D0 A/D A/D A/D A/D VSS A/D A/D A/D CE A10 E X68C75 SLIC PLCC TQFP

X68C75 SLIC® E2 Each bidirectional port consists of 8 general purpose I/O lines and 1 data strobe line. The ports also feature a configurable interrupt request output. Access to the X68C75 is accomplished through the multiplexed address/data bus of the 68HC11 type con- trollers. An internal programmable address decoder maps the internal memory and register locations into the desired address space. ARCHITECTURAL OVERVIEW The X68C75 incorporates the interface circuitry nor- mally needed to decode the control signals and demultiplex the address/data bus to provide a “seam- less” interface. The control inputs on the X68C75 are configured such that it is possible to directly connect them to the proper interface signals of the 68HC11 microcontroller. The reading of data from the chip is controlled by the R/W and E clock signals. Reading and writing of the nonvolatile memory array is analogous to RAM operation. During a write operation to either the nonvolatile memory or the control registers, the falling edge of AS latches the address present on the address bus into the X68C75, and the falling edge of E clock latches the data to be written. The nonvolatile memory of the X68C75 is internally organized as two independent arrays of 4K-bytes with the A12 input selecting which of the two planes of memory is to be accessed. While the processor is executing code out of one plane, write operations can take place in the other plane; allowing the processor to continue execution of code out of the X68C75 during a byte or page write to the device. This feature is called Concurrent Read During Write. The X68C75 also features an advanced implementation of the Software Data Protection scheme, called Block Protect, which allows the nonvolatile memory array to be treated as 8 independent sections of 1K-bytes. Each of these sections can be independently enabled for write operations. This allows segmentation of the memory contents into writable and non-writable sections, thereby, allowing certain sections of the device to be secured so that updates can only occur in a controlled environ- ment. (e.g. in an automotive application, only at an authorized service center). The Block Protect configu- ration is stored in a nonvolatile register, ensuring that the configuration data will be maintained after the device is powered-down. FUNCTIONAL DIAGRAM

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E R/W RESET IRQ 1K X 8 1K X 8 1K X 8 1K X 8 1K X 8 1K X 8 SDP DECODE CONFIG REGISTER MAPMEM. PORT SPECIAL FUNCTION REGISTERS PORT A PORT B PORT SELECT DATA I/O BUS A0–A15 I/O0–I/O7 WC E2PROM

16 X 8

X68C75 SLIC® E2 PIN DESCRIPTIONS PIN NAME I/O DESCRIPTION A15–A8 I Non-multiplexed high-order Address line inputs for the upper byte of the address. The addresses are latched when AS makes a HIGH to LOW transition. AD 7–AD 0 I/O Multiplexed lower-order Address and DATA lines. The addresses are latched when AS makes a HIGH to LOW transition. AS I Address Strobe input is used to latch the addresses present on the address lines A15–A8 and AD7– AD 0 into the device. The addresses are latched when AS transitions from HIGH to LOW. CE I The device select (CE) is an active HIGH input. This signal has to be asserted prior to AS HIGH to LOW transition in order to generate a valid internal device select signal. Holding this pin LOW and AS LOW will place the device in standby mode. The ports stay active at all times. E I The E clock is the bus frequency clock input, and is used as a data timing reference signal. When the E clock is LOW, the addresses are latched by HIGH to LOW transition on the AS pin. The E clock HIGH cycle is used for data transfers. IRQ O The IRQ is an open-drain output. It can be configured to signal latching of new data into the ports, and completion of an E2 memory write cycle. PA 7–PA 0 I/O The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select the port A I/O mode. PB 7–PB 0 I/O The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select the port B I/O mode. R/W I The R/ W signal indicates the direction of data transfers. During phase 2 (HIGH cycle) of the E clock, the R/W is HIGH for a read, and LOW for a write cycle. RESET I RESET is used to initialize the internal static registers and has no effect on the E2 memory opera- tions. The default active level is LOW, but it can be reconfigured in EEM register. SEL I The SEL input should be LOW for the device to be selected. This input is normaly tied to VSS . STRA, STRB I/O The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid transition on their strobe pins will latch into their Port Data Register the data present at the port input pins. Writing to an output port Data Register generates a pulse of fixed duration on its corresponding strobe pin. The output data presented at the output pins stay valid until the next data is written to the output port data register. WC I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to disable writes to the E2 memory. Taking the WC HIGH prior to tBLC (100µs; the time delay from the last write cycle to the start of internal programming cycle) will inhibit the write operation. 2899 PGM T01.1 The X68C75 write control input, serves as an external control over the completion of a previously initiated page load cycle. The X68C75 also features the industry standard 5V E memory characteristics such as byte or page mode write and Toggle Bit Polling. Read A HIGH to LOW transition on AS latches the address; the data will be output on the AD pins when E clock and R/W are HIGH (t ACC ). Write A write is performed by latching the address on the falling edge of AS. The R/W signal LOW while E clock is HIGH initiates a write cycle. The valid data must be present on AD 0-AD7 prior to an E clock HIGH to LOW transition. The data will be latched into the X68C75 on the falling edge of E clock. Page Write Operation The X68C75 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X68C75. Each individual write within a page write operation must conform to the byte write timing requirements. The rising edge of E clock starts a timer delaying the internal programming cycle 100µs, therefore, each successive write operation must begin within 100µs of the last byte written. The waveform on page 19 illustrates the sequence and timing requirements. Toggle Bit Polling Because the X68C75 typical write timing is less than the specified 5ms, Toggle Bit Polling has been provided to

Figure 1. Toggle Bit Polling E Control

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conform to the page write timing requirements. include writing to EE map, SFR map, and BPR. programs residing in the other blocks. lockout state will remain in the write lockout state.

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memory plane not being read. Figure 3. Sequence to Deactivate

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Figure 2. Writing with SDP Enabled

Figure 7. On-Chip Registers

0 LAM 0 RST A15 A14 A13 EEM* E2 Memory Map Register

0430 PPRA Port Pin Register A

initialized by a valid reset input signal and when the device is power cycled.

16 Bytes General Purpose SRAM

Figure 8. Setting the SFR Map Register Figure 9. Setting Program Memory Map Register

2 Memory

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where the SFR memory is mapped. will interfere with device proper operation.

2 Memory Map Register (EEM) Default = 07

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byte page where program memory will be mapped. The RST bit controls the polarity of the RESET input pin. memory plane not being read. memory plane not being read.

microcontroller at their corresponding SFR addresses.

2 Memory Map Register 38H

the source of pending interrupt. means to detect the early completion of a write cycle. Figure 10. Interrupt Status Register and port B was an input port. and port A was an input port.

map of configuration register is shown below. inputs of its PDR latch are connected to the port pins. mode using the PPR read feature. proper switching of the I/O lines. operations for both writes and reads. Figure 11. Configuration Register

1 AWO BWO DIRA DIRB STPA STPB

ured as an input, is fed to the clock input of the port latch. data also simultaneously arrives at the port output pins. and a “0” sets it to active LOW () . with the INT interrupt flag at the end of strobe pulse input. enable flags (ENA, and ENB) are set by the software. Figure 12. Block Diagram of the I/O Ports

either a direct connection or via an interrupt controller. interrupt is cleared by setting EOW to “0”. Table 1. X68C75 Interrupt Sources output, it can no longer generate any interrupts. corresponding to the interrupt flags (INTA, INTB) in ISR. cally clears the interrupt flags. polarity bit controls the PDR input latch clock signal. interrupt signal will be asserted. tage of this feature are software generated interrupts.

X68C75 SLIC® E2 X68C75 location E024H. The XSLIC software, a PC based communication driver, automates changing of the default parameters when using its SETUP option menu. The boot-firmware (SLIC) residing on the X68C75 contains a lookup table which can be accessed from the subroutine (EXEC_FUNC), located at location E120H. Two bytes are used per table entry. The EXEC_FUNC input requirements are as follows: B = Contains a function number from the following function table. The table entry at location (E14E-E14FH) is reserved for user’s application code. This function will be executed on power-up if the SLIC receives any characters other than those for the RESET (ASCII ‘R’), or ID (ASCII ‘X’) commands. This table entry can be changed to point to other code responsible for power-up initialization. This method is preferred to changing the reset vector, since the SLIC code can still be invoked upon power-up. Other functions available through the EXEC_FUNC calls are as follows: the interrupt is enabled, an external interrupt will be asserted at the completion of the internal write cycle. The interrupt is cleared by setting EOW to “0”. USING A PORT IN BIDIRECTIONAL MODE In order to use a port in bidirectional mode, it has to be configured as an open drain output port. Small pull-up resistors are required on all port output pins. Bit positions in the port data register corresponding to port inputs should contain “1”. The inputs are then read by access- ing PPR. Data is not latched into the device, so the inputs must stay valid throughout the read cycle. The port strobe pin is configured as an output and cannot be used as port latch clock input. SLIC FUNCTIONS (68HC11 Specific SLIC) The resident SLIC E 2 has designated memory spaces allocated for its use. The user’s application code should avoid using these areas as part of its code segment, otherwise it will overwrite the SLIC E 2. Version 3.0 of the X68C75 SLIC E 2 occupies 192 bytes in the upper memory bank, FF00-FFC0H, and 336 bytes in the lower bank’s address range E000-E14FH. Prior to download- ing code, assemble and link the source files using the above address information. Use memory space taken up by the SLIC E 2 as a run-time data storage, if there is no further need to modify the X68C75 SLIC E2 content. The current version of the SLIC E2 configures the 68HC11 serial port to the variable baud rate mode. It sets a timer prescalar value for a system clock rate of 8MHz. For other clock rates, the end user must recalculate timer 1 reload value for 9600 baud rate and write it into the Figure 13. SLIC E000 E150 FF00 FFC0 SLIC User’s Program/Data

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ISR & Reset Vectors FFFF FUNCTION NO. DESCRIPTION 0 - PROC_PROG Download and program a page 1 - PROC_BPR Program BPR 2 - RESET Start execution from location E000H 3 - PROC_VER Download and verify a page 4 - DUMMY Command not recognized 5 - INIT_UART Initialize UART parameters to default 6 - PROG_PG Program a page 7 - SEND_CHAR Send a character to the UART 8 - GET_CHAR Read a character from the RAM receive buffer (40H-5FH) 9 - SDP_HI_PLANE Generate SDP off sequence for upper plane 10- SDP_LO_PLANE Generate SDP off sequence for lower plane 11- USER_CODE Execute user’s code 2899 PGM T03.2 Table 2. For detailed information about the listed functions, in- cluding their input requirements, refer to the SLIC soft- ware specification document.

Figure 15. Example 2 Figure 14. Example 1 and/or other SLIC devices that Xicor manufactures. 64 x 1K pages within the memory space.

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2 memory location are not available. Figure 17. Example 4 Figure 16. Example 3

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128 I/O

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X68C75 SLIC® E2 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC VCC Current (Active) 60 mA CE = V IH, All I/O’s = Open, Other Inputs = VCC ISB1(CMOS) VCC Current (Standby) 100 µA CE = V IL, All I/O’s = Open, Other Inputs = VCC –0.3V, AS = VIL ISB2(TTL) VCC Current (Standby) 2 mA CE = V IL, All I/O’s = Open, Other Inputs = VIH, AS = VIL ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC , E = VIL VlL(3) Input LOW Voltage –1 0.8 V VIH(3) Input HIGH Voltage 2 V CC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 2.1mA, Ports (A,B) IOL = 20mA VOH Output HIGH Voltage 2.4 V I OH = –400µA 2899 PGM T06.1 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Lead Temperature *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 2899 PGM T04.1 Supply Voltage Limits X68C75 5V ±10% 2899 PGM T05.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Test Max. Units Conditions C I/O(4) Input/Output Capacitance 10 pF V I/O = 0V C IN(4) Input Capacitance 6 pF V IN = 0V

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Notes: (3) VIL min. and VIH max. are for reference only and are not tested. (4) This parameter is periodically sampled and not 100% tested. POWER-UP TIMING Symbol Parameter Max. Units tPUR (4) Power-Up to Read 1 ms tPUW (4) Power-Up to Write 5 ms

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X68C75 SLIC® E2 A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input and Output Timing Levels 1.5V 2899 PGM T09.1 EQUIVALENT A.C. TEST CIRCUIT Note: (5) This parameter is periodically sampled and not 100% tested. E Controlled Read Cycle E Controlled Read Cycle No. Symbol Parameter Min. Max. Units 1P W ASH Address Strobe Pulse Width 80 ns 2t ASL Address Setup Time 20 ns 3t AHL Address Hold Time 30 ns 4t ACC Data Access Time 120 ns 5t DHR Data Hold Time 0 ns 6t CSL CE Setup Time 7 ns 7P W EH E Pulse Width 150 ns 8t ES Enable Setup Time 30 ns 9t EH E Hold Time 20 ns 10 t RWS R/W Setup Time 20 ns 11 t HZ (5) E LOW to High Z Output 50 ns 2899 PGM T10.1 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) AS A/D0–A/D7 A8–A12 R/W AIN D OUT

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A8–A12 E 2899 ILL F20.2 1.92KΩ 100pF OUTPUT 1.37KΩ

X68C75 SLIC® E2 E Controlled Write Cycle No. Symbol Parameter Min. Max. Units 1P W ASH Address Strobe Pulse Width 80 ns 2t ASL Address Setup Time 20 ns 3t AHL Address Hold Time 30 ns 4t DSW Data Setup Time 50 ns 5t DHW Data Hold Time 30 ns 6t CSL CE Setup Time 7 ns 7P W EH E Pulse Width 120 ns 8t ES Enable Setup Time 30 ns 9t RWS R/W Setup Time 20 ns 10 t EH E Hold Time 20 ns 11 t WC Write Cycle Time 5 ms 12 t BLC Byte Load Time (Page Write) 0.5 100 µs

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Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. AS A/D0–A/D7 A8–A12 R/W AIN D IN

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A8–A12 E 4 5

X68C75 SLIC® E2 Page Write Timing Sequence for E Controlled Operation CE AS A/D0–A/D7 A8–A12 E R/W AIN D IN A12=n OPERATION BYTE 0 BYTE 1 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION 2899 ILL F04.1 AIN D IN A12=n AIN D IN A12=n AIN D IN A12=n AIN D IN A12=x AIN ADDR AIN Next Address 12 11

X68C75 SLIC® E2 Port Read Diagram PORT READ TIMING No. Symbol Parameter Min. Max. Units 1t SVSX Strobe Pulse Width 80 ns 2t IS Data Port Setup 20 ns 3t IH Data Port Hold Time 30 ns 4t SVIV Interrupt Request to Strobe 50 ns 5t IAD IRQ to AS 0 ns 6P W ASH AS Pulse Width 80 ns 7t RXIX E to IRQ High 30 ns 8t ASL Address setup time 20 ns 9t AHL Address hold time 30 ns 10 t ASE AS to E High 30 ns 11 t ACCE E Access Time 120 ns 12 t RWS R/W Setup Time 30 ns 13 t RWH R/W Hold time 10 ns 2899 PGM T12.1 STRA/STRB * PA7:0/PB7:0 IRQ 2899 ILL F26.2 AS R/W A15–A8 E AD7–AD0 4 7 8 9 8 9 11 INTERRUPT RECOGNIZED PORT ADDRESS A7-A0 DATA VALID NOTE: *Figure shows active HIGH strobes. DATA VALID (IN)

X68C75 SLIC® E2 Port Write Diagram PORT WRITE TIMING No. Symbol Parameter Min. Max. Units 1P W ASH AS Pulse Width 80 ns 2t WCS Write Chip Select Setup Time 20 ns 3t WH Write Pulse Hold Time 10 ns 4t WV Write Pulse Valid to E Rise 30 ns 5t AVLL Address Setup Time 20 ns 6t LLAX Write Address Hold Time 30 ns 7t DVWH Data Setup Time 50 ns 8t WHDX Data Hold Time 10 ns 9t SVSX Strobe Pulse Width 120 ns 10 t QVSV Strobe Access Time 40 ns 11 t POS Port Output Setup Time 40 ns

12 P WEH E Clock Pulse Width 150 ns

2899 PGM T13.1 A15–A8 CE AS R/W E AD7–AD0 STRA/STRB* (OUT) PA7:0 / PB7:0 2899 ILL F27.1 2 6 7 8 ADDRESS A15-A8 ADDRESS A7-A0 NEW PORT DATA VALIDPREVIOUS PORT DATA NOTE: *Figure shows active HIGH strobes. DATA VALID

X68C75 SLIC® E2 LAM (Latch Address Mode) Diagram LAM TIMING No. Symbol Parameter Min. Max. Units 1t LHLL AS Pulse Width 80 ns 2t AVLL Address Setup Time 20 ns 3t LLAX Address Hold Time 30 ns 4t POS Port Output Setup Time 20 ns 2899 PGM T14.1 A15–A8 AS AD7–AD0 PB7:0

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ADDRESS A7–A0

X68C75 SLIC® E2 PACKAGING INFORMATION 3926 FHD F43.1 NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. P ACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 2.480 (62.99) 2.385 (60.58) 2.300 (58.42) REF. PIN 1 INDEX 0.195 (4.95) 0.125 (3.18) 0.030 (0.76) 0.015 (0.38) PIN 1 SEATING PLANE 0.070 (17.78) 0.030 (7.62) 0.580 (14.73) 0.040 (1.02) 15° 48-LEAD PLASTIC DUAL IN-LINE P ACKAGE TYPE P TYP. 0.010 (0.25)

X68C75 SLIC® E2 PACKAGING INFORMATION 0.500 (12.70) REF. 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) PIN 1 0.500 (12.70)REF. 0.050 (1.27)REF. 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) 0.021 (0.63) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) 0.032 (0.81) 0.026 (0.66) 0.156 (3.96) 0.145 (3.68) 0.011 (0.28) 0.009 (0.23) 0.180 (4.57) 0.165 (4.19) 0.110 (2.79) 0.100 (2.54) 0.020 (0.51) SEATING PLANE –0.004 LEAD CO – PLANARITY 44-PIN PLASTIC LEADED CHIP CARRIER P ACKAGE TYPE J NOTES: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONL Y 3926 ILL F29.2

X68C75 SLIC® E2 PACKAGING INFORMATION GAGE PLANE 0.25 C 7°–0° 3926 ILL F36.4 He D e b Hd E NOTES: 1. GAGE PLANE DIMENSION IS IN MM. 2. LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM. 44-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L PIN 1 DIM INCHESMILLIMETERS MIN MAX MIN MAX b c D E e Hd He 0.05 1.35 0.22 0.090 9.90 9.90 11.90 11.90 0.15 1.45 0.38 0.200 10.10 10.10 12.10 12.10 0.002 0.053 0.009 0.004 0.390 0.390 0.468 0.468 0.006 0.057 0.015 0.008 0.398 0.398 0.476 0.476 1.00 TYP 0.039 TYP 0.80 TYP 0.031 TYP

X68C75 SLIC® E2

ORDERING INFORMATION

Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 48-Lead Plastic DIP J = 44-Lead PLCC L = 44-Lead TQFPLIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.