X60250V8I

X60250 INTERSIL | Alldatasheet

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FN8146.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X60250 Micro Power Programmable Voltage Reference

FEATURES

• 1.25V 1.0%, 20ppm/°C Tempco Reference
• Adjustable to ±0.25% Over the 0 to 1.25V Range
• 8 bit, 100kΩ XDCP on-chip
• Programmable Resolution of 4.9mV (255 steps)
• Extra Matched 100kΩ Resistor Available for Increased Resolution Over a Smaller Range
• 2.7V to 5.5V Supply Range
• 2-Wire Interface for Programming Reference Setting
• Low Supply Current: 12µA in Normal Mode
• 8-pin TSSOP Package
• Programmable Reference
• NV Memory
• Pb-Free Plus Anneal Available (RoHS Compliant) PROGRAMMABLE VOLTAGE REFERENCE APPLICATIONS
• Sensor Bias
• Variable DAC reference
• Linear Voltage Regulators
• DC/DC converters
• Voltage comparators
• Motor controllers
• Amplifier biasing

DESCRIPTION

The Intersil X60250 combines a temperature compensated voltage reference with a Intersil Digitally Controlled Potentiometer (XDCP) to provide a precision adjustable reference with a range of 0.0V to 1.25V. The device includes a serial bus interface to enable in-circuit programming of the reference voltage. The XDCP contains a resistor chain with 255 taps to provide 8 bits of digital adjustment to the reference voltage. Non-volatile storage retains the digital wiper setting, for permanent reference programming. An additional matched 100k Ω resistor is available to increase resolution of the output voltage while retaining accuracy. IC BLOCK DIAGRAM VCC VREFOUT SCL SDA GND V REFL VOUT 100K 100kΩ 1.25V Reference Serial Interface EE PROM

256 Tap DCP

Data Sheet September 14, 2005

2 FN8146.1 September 14, 2005 PIN CONFIGURATION PIN ASSIGNMENTS

Ordering Information

(V) RESOLUTION TEMP RANGE (°C) PACKAGE X60250V8I 60250 I 1.250 8 bits -40 to 85 8 Ld TSSOP X60250V8IZ (Note) 60250I Z 1.250 8 bits -40 to 85 8 Ld TSSOP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. TSSOP Symbol Description 1V REFL DCP and auxiliary resistor reference input 2V CC Positive Power Supply 3V REFOUT Bandgap Reference Output 4V OUT DCP Wiper Output 5R 1 Auxiliary resistor input

6 GND Ground

7 SDA Serial Data Input/Output

8 SCL Serial Clock Input

3 FN8146.1 September 14, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on V RECOMMENDED OPERATING CONDITIONS COMMENTS Absolute Maximum Ratings indicate limits beyond which permanent damage to the device and impaired reliability may occur. These are stress ratings provided for information only and f unctional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. For guaranteed specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test con- ditions listed. Some performance characteristics may de- grade when the device is not operated under the listed test conditions.

ELECTRICAL CHARACTERISTICS

(Over operating conditions unless otherwise specified. I OUT = 12.5 µA, R1 = N/C (Floating).) Min Max Temperature -40°C +85°C Supply Voltage 2.7V 5.5V ANALOG PARAMETERS Symbol Parameter Limits Test ConditionsMin. Typ. (1) Max. Unit Power Supply VCC Supply Voltage Range 2.7 3.0 5.5 V IQ Supply Current VCC = 2.7V VCC = 3V VCC = 5.5V Write µA R L=0, VREFL, VOUT, RAUX = floating IQ(NV) Non-Volatile Supply Current VCC = 2.7V VCC = 3V VCC = 5.5V 600 1100 1300 µA R L=0, VREFL, VOUT, RAUX = floating Reference Output Voltage DC Parameters VREFOUT Output Voltage 1.237 1.250 1.263 V T A = 25°C VREFL DCP and auxilliary resistor reference input GND V REFOUT V TCOref Temperature coefficient of VREF output voltage PSRR Power Supply Rejection 55 66 dB (6) IOUT Output Current Sourcing Sinking 1 400 µA (2) ROUT Output Impedance 1 2.5 Ω Given by ROUT = (∆VREF/∆IOUT) (2) ISC Short Circuit Current Sourcing Sinking mA At 5.5V C L Load Capacitance 0.001 0.003 µF Reference output stable for all CL up to specifications (2) X60250

4 FN8146.1 September 14, 2005 DIGITAL PARAMETERS EEPROM PARAMETERS (Erase at VCC = 5.0 V min, T = 25°C) CAPACITANCE AC Parameters VN Output Voltage Noise 100 200 µVP-P µVRMS 0.1Hz to 10Hz (2) 10Hz to 10kHz (2) Power-on Response 250 µs 1% Settling (2) Line Ripple Rejection 60 dB V DD = 3V ±100mV, f = 120 Hz (2) Reference DCP Resolution 8 bits RTOT End to end resistance 85 100 115 k Ω RW Wiper Resistance VCC = 2.7V VCC = 3V 600 5000 1200 Ω (2) Absolute Linearity (INL) ±0.2 LSB Relative Linearity (DNL) ±0.1 LSB R TOT Temperature Coeff. ±300 ppm/°C Ratiometric Temp. Coeff. ±20 ppm/°C RAUX (Auxiliary Resistor) RTOT End to end resistance 85 100 115 k Ω RTOT Temperature Coeff. ±300 ppm/°C R L=0, VREFL, VOUT, RAUX = floating DCP Matching Tolerance 0.1 % DCP Matching Temp. Coeff. ±20 ppm/°C Symbol Parameter Limits Test ConditionsMin. Typ. (1) Max. Unit ILI Input Leakage Current 2 µA V IN = GND to VCC ILO Output Leakage Current 2 µA V OUT = GND to VCC VIL Input Low Voltage 0 V CC x 0.2 V VIH Input High Voltage V CC x 0.7 V CC V CIN Input Capacitance 5 pF VOL Output Low Voltage 0 10 %V DD IOL = 100 µA (2) VOH Output High Voltage 90 100 %V DD IOH = 100 µA (2) CL Output Load 100 pF (2) Parameter Min. Units Write Cycle Endurance 100,000 Cycles per bit Symbol Test Max. Units Test Conditions CIN/OUT Input/Output capacitance (SDA) 8 pF V OUT = 0V (2) CIN Input capacitance (SCL) 6 pF V IN = 0V (2) ANALOG PARAMETERS (CONTINUED) Symbol Parameter Limits Test ConditionsMin. Typ. (1) Max. Unit X60250

5 FN8146.1 September 14, 2005 A.C. TEST CONDITIONS AC SPECIFICATIONS TIMING DIAGRAMS Bus Timing Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing threshold level V CC x 0.5 External load at pin SDA 2.3k Ω to VCC and 100 pF to VSS Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs (2) 50 ns tAA SCL LOW to SDA Data Out Valid (2) 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start (2) 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time (2) 0.6 µs tDH Data Output Hold Time (2) 50 ns tR SDA and SCL Rise Time (2, 3) 20 +.1Cb 300 ns tF SDA and SCL Fall Time (2, 3) 20 +.1Cb 300 ns Cb Capacitive load for each bus line (2, 3) 400 pF tSU:STO tHIGH tSU:STA tHD:STA tHD:DATtSU:DAT SCL SDA IN SDA OUT tF tLOW tHD:DAT tR tDHtAA tBUF tHD:STO tBUF X60250

6 FN8146.1 September 14, 2005 WRITE CYCLE TIMING POWER-UP TIMING NONVOLATILE WRITE CYCLE TIMING Notes: (1) Typical values are for T A = 25°C and VCC = 3.0V (2) This parameter is guaranteed by characterization. (3) Cb = total capacitance of one bus line in pF. (4) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. (5) Over the specified temperature range. Temperature coeffi cient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40°C to +85°C = 125°C. TCOref = [Max V(VREF) - Min V(VREF)] × SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min. Max. Unit ∆VCC/∆tV CC Power-up rate (2) 0.2 50 V/ms tPUR Time from Power-up to Read (2) 1m s tPUW Time from Power-up to Write (2) 5m s Symbol Parameter Min. Typ. Max. Unit tWC Write Cycle Time (4) 51 0 m s X60250

7 FN8146.1 September 14, 2005 FUNCTIONAL DESCRIPTION The X60250 combines a micropower precision reference with an 8-bit, 256 tap digitally controlled 100k Ω potentiometer (DCP) which allows nonvolatile setting of an output reference voltage. When normally configured with the V REFL pin tied to ground, the device provides an output range of 0V to 1.25V with 4.90mV resolution. The device can also be configured with an optional 100kΩ series resistor to ground, which effectively halves the output voltage range while doubling the resolution. Grounding the R 1 pin while floating the VREFL pin places the device in this mode. Output voltage setting accuracy can be as high as 0.10% while permitting adjustment from 0.625V to 1.25V (2.45mV resolution). Reference Section The reference is designed to provide an accurate, low tempco voltage source while requiring less than 12µA (typical) of supply current. This supply current is for the reference section only. Keep in mind that the DCP will increase supply current draw by VREF/RTOTAL (typically 1.25/100k or 12.5µA). The total current drawn by the adjustable reference circuit will be less than 25µA (typically). The reference output has a typical impedance of 1Ω and can provide up to 400µA of load current. It is intended to drive the resistive load of the DCP, which is a minimum of 85kΩ, but can also be used to drive off chip circuitry provided the loading does not exceed the 400µA maximum. Also, highly capacitive loads can make the reference oscillate, so no more than 2000pF should be placed directly on the output of the V REFOUT pin. The reference output produces about 200µV RMS of noise (10kHz bandwidth) due to its micropower design. This is easily reduced in normal applications, as shown in the applications section for optimizing circuits for reducing output noise levels. DCP Section The 256 tap DCP has an 8-bit nonvolatile wiper control register which controls which tap is selected. The register is changed by performing a serial data write to its address (0h, see Serial Interface section). The resulting wiper position will produce an output voltage at V OUT, depending on whether the DCP VREFL is grounded or the R1 pin is grounded. The wiper consists of CMOS transistors and has a finite resistance, typically 600Ω at VCC = 5V (this parameter increases with decreasing VCC). The wiper resistance will produce errors in reference circuits due to I-R drops if current flows through the wiper. However, typically these circuits will have the wiper connected to a high impedance comparator or amplifier input which results in very small wiper currents and thus only a small output voltage error. If the X60250 is used with the wiper connected to V REFL to produce a current source, care must be taken to avoid exceeding the maximum output current of the reference (typically 400µA). Power-Up considerations The X60250 contains EEPROM nonvolatile storage cells which are recalled during power-up. This recall process works best with power supply (V CC) ramping that is monotonic and free of excessive glitches (<100mV disturbances give best results). The ramp rate spec should be adhered to, although the most sensitive part of recall is between V CC = 1.0V and 2.5V. Effort should be made to make sure the device receives a power-up ramp between those voltage levels that meet the ramp rate spec and have no glitches. Recall of the stored wiper position happens in < 1ms from V CC reaching 2.5V. Note that any excursions of VCC below 2.5V, although temporary, can cause the wiper to be loaded with the midpoint value (80h) until V CC recovers to its normal voltage. Register Organization There are 2 nonvolatile registers and 1 volatile register available for storage and recall via the serial bus. They contain the current wiper position, a general purpose data register and a status register. The wiper register is nonvolatile and is at address 0h and contains 8 bits, with the 00h setting corresponding to the tap position nearest V REFL, and the FFh setting nearest to VREFOUT. The general purpose register is nonvolatile and is at address 1h, and contains 8 bits for use as scratchpad memory or serial number information. The Status register is volatile and is at address 7h. It has one active bit, D3, which is the WEL bit. This bit must be set to 1 berfore any nonvolatile writes are performed to the other registers. See the register information on the next page. X60250

8 FN8146.1 September 14, 2005 X60250 REGISTER BIT MAP REGISTER DESCRIPTIONS REGISTER 0 (NONVOLATILE) This register is used to hold the DCP wiper position, which is given by: REGISTER 1 (NONVOLATILE) This 8 bit register is used for general storage such as date code, temp setting, etc. STATUS REGISTER Addr D7 D6 D5 D4 D3 D2 D1 D0 0D 7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 1D 7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)

70000 W E L 000

Reg Nonvolatile Description Y Y N V OUT wiper setting General Purpose data storage register Status register Bit Value Description D - D4 D2 - D0 0 - 1 Must remain 0 WEL bit Must be programmed to "1" for Reg 0 or 1 EEPROM write. When accessing, only WEL bit may be changed Must remain 0 VOUT VREF Code X60250

10 FN8146.1 September 14, 2005 X60250 BUS INTERFACE INFORMATION Slave Address, Address Byte, and Data Byte The byte communication format for the serial bus is shown in Figure 1 on the previous page. The first byte, BYTE 0, defines the device identifier, 0101 in the upper half; and the device slave address in the low half of the byte. The slave address is set to 0. The next byte, BYTE 1, is the Address Byte. The Address Byte identifies a unique address for the Status or Control Registers as shown in the R egister Descriptions table. The following byte, Byte 2, is the byte used for READ and WRITE operations. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. On power- up, the SCL pin must be brought LOW prior to the START condition. See Figure 3. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH followed by a HIGH to LOW transistion on SCL. After going LOW, SCL can stay LOW or return to HIGH. See Figure 3. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for: – The Slave Address Byte when the Device Identifier and/or Select bits are incorrect – The 2nd Data Byte of a Status Register Write Oper- ation (only 1 data byte is allowed) Pin Descriptions V REFOUT Reference voltage output. The 1.25V bandgap reference output (V REF) is available at this pin for application to other circuits. Maximum output current is 400µA. The V REFOUT pin also connects to the Rh terminal of the 256-tap DCP. VOUT DCP Wiper Output. This pin functions as the wiper of the DCP, and can be used as a variable voltage source for voltages between GND and V REF. Since it is connected to the DCP resistor, any loads on this pin must be high impedance for best performance. R Auxiliary Resistor Input. The R1 pin is connected to one end of a 100kΩ resistor (R1) which closely matches the DCP resistance. The other end of R1 is tied to the RREFL terminal of the DCP. When R1 is grounded and VREFL is left open, the output voltage range of VOUT will be from VREF/2 to VREF, and the effective resolution (mV/step) of the Reference control is doubled. R1 should be left open if not used. GND This pin is common for the VREF output and for control signal inputs. SDA Serial Data Input/Output. Bidirectional pin used for serial data transfer. As an output, it is open drain and may be wire-ored with any number of open drain or open collector outputs. A pullup resistor is required and the value is dependent on the speed of the serial data bus and the number of outputs tied together. SCL Serial Clock Input. Accepts a clock signal for clocking serial data into and out of the device. V REFL DCP and Auxiliary Resistor Input. This pin is connected to one end of the 256-tap DCP, and also to one end of the 100kΩ auxiliary resistor. When connected to ground, V OUT range will be from 0V to V REF. When left open and R1 is connected to ground, the voltage at this pin will be from VREF/2 to VREF. X60250

13 FN8146.1 September 14, 2005 TYPICAL PERFORMANCE CHARACTERISTIC CURVES Icc vs Vcc 10.00E-6 15.00E-6 20.00E-6 25.00E-6 30.00E-6 35.00E-6 40.00E-6 45.00E-6 50.00E-6 Vcc (V) Icc (A) Icc (-40C) Icc (25C) Icc (85C) VRefout vs Temperature (2 representative units) 1.24620 1.24670 1.24720 1.24770 1.24820 1.24870 1.24920 1.24970 1.25020 1.25070 1.25120 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) VRefout (V) Refout Rf t VRefout vs Vcc 1.249E+0 1.250E+0 1.251E+0 1.252E+0 1.253E+0 1.254E+0 1.255E+0 1.256E+0 1.257E+0 Vcc (V) VRefout (V) Refout (-40C) Refout (25C) Refout (85C) Vref Output Voltage Noise, 0.1Hz to 10Hz Filter = 1 zero at 0.1Hz 2 poles at 10Hz Vertical = 50µV/div Horizontal = 1 sec/div INL -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0 50 100 150 200 250 Tap Position ERROR (LSB) DNL -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0 50 100 150 200 250 Tap Position ERROR (LSB) VREF Output Noise Spectrum 10 100 1000 10000 Frequency Noise, uV/rt*Hz IREFOOUT vs VREFOUT 1.2450 1.2460 1.2470 1.2480 1.2490 1.2500 1.2510 1.2520 1.2530 1.2540 1.2550 IREFOUT (mA) VREFOUT (V) +25 deg C -40 deg C +85 deg C X60250

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8146.1 September 14, 2005 PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Code V8 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical X60250