X5649S14-2.7

X5648 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Renesas
• PDF pages: 18

Technical content

FN8136 Rev 0.00 Page 1 of 18 March 17, 2005 FN8136 Rev 0.00 March 17, 2005 X5648, X5649 (Replaces X25648, X25649) CPU Supervisor with 64Kbit SPI EEPROM DATASHEET

FEATURES

• L o w VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock ™ protection —In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages —14-lead SOIC, 8-lead PDIP

DESCRIPTION

These devices combine three popular functions, Power- on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions by holding RESET /RESET active when VCC falls below a minimum VCC trip point. RESET /RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard V TRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision. BLOCK DIAGRAM Data Register Command Decode & Control Logic SI SO SCK CS VCC Reset Timebase Power-on and Generation VTRIP RESET/RESET Reset Low Voltage Status Register Protect Logic 16Kbits 16Kbits 32Kbits EEPROM Array WP X5648 = RESET X5649 = RESET

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 2 of 18 March 17, 2005 PIN CONFIGURATION PIN DESCRIPTION Pin (PDIP) Pin (SOIC) Name Function 12 , 3 C S Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. 24 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 59 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 61 0 S C K Serial Clock. The serial clock controls the serial bus timing for data input and out- put. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

35 W P

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits.

46 V SS Ground

8 12, 13 V CC Supply Voltage 7 11 RESET / RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will re- main active until VCC rises above the minimum VCC sense level for 200ms. RE- SET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power- up at about 1V and remains active for 200ms after the power supply stabilizes. 1, 7, 8, 14 NC No internal connections X5648/49 X5648/49 8-Lead PDIP CS WP SO RESET/RESET VCC 14-Lead SOIC CS VSS NC V CC SI NC CS NC VCC VSS SCK SI NC SO WP RESET/RESET SCK

Figure 3. VTRIP Programming Sequence Flow Chart

Figure 4. Sample VTRIP Reset Circuit allowing operation on a simple four-wire bus. and a minimum data retention of 100 years. must be LOW during the entire operation. again to resume operations where left off. tion of a valid write cycle. Table 1. Instruction Set Note: *Instructions are shown MSB in left most position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix set HIGH and when WEL = 0 the latch is reset LOW. one quarter, one half, all or none of the EEPROM array. all status register write operations. bits from inadvertent corruption. ables subsequent write attempts to the status register. grounded and still be able to program the status register. select the device followed by the 8-bit RDSR instruction. status register sequence (Figure 2).

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

Figure 5. Read EEPROM Array Sequence tion, the write operation will be ignored. have been previously written. not be completed (Figure 4). – The device is in the low power standby state. an active state and receive an instruction. – The write enable latch is reset. to start a nonvolatile write cycle.

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 10 of 18 March 17, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any Pin with respect to VSS ... -1.0V to +7V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) CAPACITANCE T A = +25°C, f = 1MHz, VCC = 5V Notes: (1) V IL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Unit Test ConditionsMin. Typ. Max. ICC1 VCC write current (active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ICC2 VCC read current (active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ISB VCC standby current WDT = OFF 1µ A C S = VCC, VIN = VSS or VCC, VCC =5 . 5 V ILI Input leakage current 0.1 10 µA V IN = VSS to VCC ILO Output leakage current 0.1 10 µA V OUT = VSS to VCC VIL(1) Input LOW voltage -0.5 V CC x 0.3 V VIH(1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < V CC  3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V V CC  2V, IOL = 0.5mA VOH1 Output HIGH voltage V CC - 0.8 V V CC > 3.3V, IOH = –1.0mA VOH2 Output HIGH voltage V CC - 0.4 V 2V < V CC  3.3V, IOH = –0.4mA VOH3 Output HIGH voltage V CC - 0.2 V V CC  2V, IOH = -0.25mA VOLS Reset output LOW voltage 0.4 V I OL = 1mA Symbol Test Max. Unit Conditions COUT(2) Output capacitance (SO, RESET/RESET) 8 pF V OUT = 0V CIN(2) Input capacitance (SCK, SI, CS, WP)6 p F V IN = 0V RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Voltage Option Supply Voltage -2.7 or -2.7A 2.7V to 5.5V Blank or -4.5A 4.5V-5.5V

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 11 of 18 March 17, 2005 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing Serial Input Timing Output 100pF 4.6k RESET/RESET 30pF 2.06k 3.03k Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 250 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) Input rise time 100 ns tFI(3) Input fall time 100 ns tCS CS deselect time 500 ns tWC(4) Write cycle time 10 ms SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 12 of 18 March 17, 2005 Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Power-Up and Power-Down Timing Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tDIS Output disable time 250 ns tV Output valid from clock low 250 ns tHO Output hold time 0 ns tRO(3) Output rise time 100 ns tFO(3) Output fall time 100 ns SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG RESET (X5648) RESET (X5649) VCC tPURST tPURST tR tF tRPD

0 Volts

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 13 of 18 March 17, 2005 RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5648-4.5A, X5648-4.5A Reset trip point voltage, X5648, X5649 Reset trip point voltage, X5648-2.7A, X5649-2.7A Reset trip point voltage, X5648-2.7, X5649-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V VTH VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV tPURST Power-up reset time out 100 200 280 ms tRPD(5) VCC detect to reset/output 500 ns tF(5) VCC fall time 100 µs tR(5) VCC rise time 100 µs VRVALID Reset valid VCC 1V SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 14 of 18 March 17, 2005 VTRIP Reset Conditions VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK VTRIP program voltage setup time 1 µs tVPH SCK VTRIP program voltage hold time 1 µs tP VTRIP program pulse width 1 µs tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms tVPO SCK VTRIP program voltage off time before next cycle 0 ms VP Programming voltage 15 18 V VTRAN VTRIP programed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP) (programmed at 25°C) -25 +25 mV Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP program variation after programming (0 - 75°C). (programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC* *VCC > Programmed VTRIP

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 15 of 18 March 17, 2005 TYPICAL PERFORMANCE Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer Off (VCC = 3V, 5V) -40 25 90 Temp (°C) Isb (µA) VCC Supply Current vs. Temperature (ISB) VTRIP vs. Temperature (programmed at 25°C) tPURST vs. Temperature 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 85 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 200 195 190 185 180 175 170 165 160 -40 25 90 Degrees °C 205 Time (ms)

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 16 of 18 March 17, 2005 PACKAGING INFORMATION NO TE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane

X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 Page 17 of 18 March 17, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.020 (0.51) Pin 1 Pin 1 Index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-Lead Plastic, SOIC, Package Code S14 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"T ypical 0.050"Typical 0.030" Typical

14 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45°

FN8136 Rev 0.00 Page 18 of 18 March 17, 2005 X5648, X5649 (Replaces X25648, X25649) Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners.

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) 14L SOIC 0-70°C X5648S14-4.5A X5649S14-4.5A -40-85°C X5648S14I-4.5A X5649S14I-4.5A 14L SOIC 0-70°C X5648S14 X5649S14 -40-85°C X5648S14I X5649S14I Blank = 14-Lead SOIC P = 8 Pin DIP Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0 WX5648/49 X