X5645

X5643 INTERSIL | Alldatasheet

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Technical content

FN8135.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X5643, X5645 (Replaces X25643, X25645) CPU Supervisor with 64Kbit SPI EEPROM

FEATURES

• Selectable watchdog timer L o w VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V  Determine watchdog or low voltage reset with a volatile flag bit  Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read  64Kbits of EEPROM  Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock ™ protection —In circuit programmable ROM mode  2MHz SPI interface modes (0,0 & 1,1)  Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)  2.7V to 5.5V and 4.5V to 5.5V power supply operation  Available packages —8-lead PDIP, 14-lead SOIC

DESCRIPTION

These devices combine four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers sys- tem cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcon- troller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be repro- grammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS /WDI VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP RESET /RESET Reset Low Voltage Status Register Protect Logic 16Kbits 16Kbits 32Kbits EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic X5643 = RESET X5645 = RESET Data Sheet July 18, 2005

2 FN8135.1 July 18, 2005 PIN CONFIGURATION 8-Lead PDIP CS /WDI WP SO RESET /RESET 14-Lead SOIC SO WP RESET /RESET SCK SI NC V CC NC X5643/45 SCK SI CS /WDI NC X5643/45 NC VCC VSS CS /WDI VCC VSS Pin PDIP Pin SOIC Pin TSSOP Name Function 1 2 & 3 2 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the de- vice will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET /RESET going active. 24 3 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 59 1 3 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 61 0 1 4S C K Serial Clock. The serial clock controls the serial bus timing for data input and out- put. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 35 7 W P Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits. 46 8 V SS Ground 8 12 & 13 19 V CC Supply Voltage 7 11 18 RESET / RESET Reset Output. RESET /RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET /RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out pe- riod. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-up at about 1V and remains active for 200ms after the power supply stabilizes. 1, 7, 8, 1, 4-6, 9-12, 15-17, 20 NC No internal connections X5643, X5645

Figure 3. VTRIP Programming Sequence Flow Chart

Figure 4. Sample VTRIP Reset Circuit EEPROM array with Intersil’s block lock protection. cycles and a minimum data retention of 100 years. with data being clocked in on the rising edge of SCK. must be LOW during the entire operation. it again to resume operations where left off. after the completion of a valid Write Cycle. “0”, no write is in progress. Table 1. Instruction Set Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix block lock protection of that portion of memory. programmed with the WRSR instruction. a watchdog time out or power failure. HIGH disables all status register write operations. bits from inadvertent corruption. disables nonvolatile writes to the device’s status register.

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

Figure 5. Read EEPROM Array Sequence ables subsequent write attempts to the status register. changes now require a hardware change. EEPROM array sequence (Figure 1). the read status register sequence (Figure 2). then the WREN instruction is clocked into the device. WREN instruction, the write operation will be ignored. that may have been previously written. will not be completed (Figure 4).

10 FN8135.1 July 18, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Unit Test ConditionsMin. Typ. Max. ICC1 VCC write current (active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ICC2 VCC read current (active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ISB1 VCC standby current WDT=OFF 1µ A C S = VCC , VIN = VSS or VCC , VCC = 5.5V ISB2 VCC standby current WDT=ON 50 µA CS = VCC , VIN = VSS or VCC , VCC = 5.5V ISB3 VCC standby current WDT=ON 20 µA CS = VCC , VIN = VSS or VCC , VCC = 3.6V ILI Input leakage current 0.1 10 µA V IN = VSS to VCC ILO Output leakage current 0.1 10 µA V OUT = VSS to VCC VIL(1) Input LOW voltage -0.5 V CC x 0.3 V VIH(1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < V CC ≤ 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V V CC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH voltage V CC - 0.8 V V CC > 3.3V, IOH = -1.0mA VOH2 Output HIGH voltage V CC - 0.4 V 2V < V CC ≤ 3.3V, IOH = -0.4mA VOH3 Output HIGH voltage V CC - 0.2 V V CC ≤ 2V, IOH = -0.25mA VOLS Reset output LOW voltage 0.4 V I OL = 1mA RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Device Option Supply Voltage -2.7 or -2.7A 2.7V to 5.5V Blank or -4.5A 4.5V-5.5V X5643, X5645

11 FN8135.1 July 18, 2005 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT AT 5V V CC A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing Symbol Test Max. Unit Conditions C OUT (2) Output Capacitance (SO, RESET/RESET) 8 pF V OUT = 0V C IN(2) Input Capacitance (SCK, SI, CS, WP)6 p F V IN = 0V Output 100pF 4.6kΩ RESET/RESET 30pF 2.06kΩ 3.03kΩ Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 250 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) Input rise time 100 ns tFI(3) Input fall time 100 ns tCS CS deselect time 500 ns tWC (4) Write cycle time 10 ms X5643, X5645

12 FN8135.1 July 18, 2005 Serial Input Timing Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tDIS Output disable time 250 ns tV Output valid from clock low 250 ns tHO Output hold time 0 ns tRO (3) Output rise time 100 ns tFO (3) Output fall time 100 ns SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG X5643, X5645

13 FN8135.1 July 18, 2005 Power-Up and Power-Down Timing RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. CS /WDI vs. RESET/RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5643-4.5A, X5643-4.5A Reset trip point voltage, X5643, X5645 Reset trip point voltage, X5643-2.7A, X5645-2.7A Reset trip point voltage, X5643-2.7, X5645-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V V TH VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV tPURST Power-up reset time out 100 200 280 ms tRPD (5) VCC detect to reset/output 500 ns tF(5) VCC fall time 100 µs tR (5) VCC rise time 100 µs VRVALID Reset valid VCC 1V RESET (X5643) RESET (X5645) VCC tPURST tPURST tR tF tRPD

0 Volts

X5643, X5645

14 FN8135.1 July 18, 2005 RESET /RESET Output Timing VTRIP Set Conditions VTRIP Reset Conditions Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec tCST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 300 ms SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC * *VCC > Programmed VTRIP X5643, X5645

15 FN8135.1 July 18, 2005 VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK V TRIP program voltage setup time 1 µs tVPH SCK V TRIP program voltage hold time 1 µs tP VTRIP program pulse width 1 µs tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms tVPO SCK V TRIP program voltage off time before next cycle 0 ms VP Programming voltage 15 18 V VTRAN VTRIP programed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) -25 +25 mV Vtr VTRIP Program Voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. X5643, X5645

16 FN8135.1 July 18, 2005 TYPICAL PERFORMANCE Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer Off (VCC = 3V, 5V) -40 25 90 Temp (°C) Isb (µA) VCC Supply Current vs. Temperature (ISB )t WDO vs. Voltage/Temperature (WD1, 0 = 1, 1) VTRIP vs. Temperature (programmed at 25°C) t WDO vs. Voltage/Temperature (WD1, 0 = 1, 0) tPURST vs. Temperature t WDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 90°C 25°C -40°C Reset (seconds) Voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 85 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 1.7 5.2 Reset (seconds) Voltage 2.4 3.1 3.8 4.5 90°C 25°C -40°C 200 195 190 185 180 175 170 165 160 -40 25 90 Degrees °C 205 Time (ms) 90°C 25°C -40°C 200 195 190 185 180 175 170 165 160 205 Reset (seconds) Voltage X5643, X5645

17 FN8135.1 July 18, 2005 PACKAGING INFORMATION NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane X5643, X5645

18 FN8135.1 July 18, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.020 (0.51) Pin 1 Pin 1 Index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-Lead Plastic Small Outline Gullwing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

14 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° X5643, X5645

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8135.1 July 18, 2005

Ordering Information

RESET (Active LOW) Part Number RESET (Active HIGH) 14L SOIC 0-70°C X5643S14-4.5A X5645S14-4.5A -40-85°C X5643S14I-4.5A X5645S14I-4.5A 14L SOIC 0-70°C X5643S14 X5645S14 -40-85°C X5643S14I X5645S14I P = 8-Lead PDIP S14 = 14 Lead SOIC Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0 WX5643/45 X X5643, X5645