X55060V20-2.7A

X55060 INTERSIL | Alldatasheet

Document overview

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Technical content

FN8133.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PRELIMINARY X55060 64K Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

FEATURES

• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages —User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to V CC = 1V
• System battery switch-over circuitry
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<30µA max standby current, watchdog off
• Selectable watchdog timer
• 64Kbits of EEPROM
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect none(0), or all of EEPROM array with programmable Block Lock ™ protection —In circuit programmable ROM mode
• Minimize EEPROM programming time —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 10MHz SPI interface modes (0,0 & 1,1)
• 2.7V to 5.5V power supply operation
• Available packages — 20-lead TSSOP

DESCRIPTION

This device combines power -on reset control, battery switch circuit, watchdog timer, supply voltage supervi- sion, secondary voltage supervision, block lock protect and serial EEPROM in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode, Test & Control Logic SI SO SCK CS VCC Reset & Watchdog Timebase Power-on, GenerationVCC Monitor RESET Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP

512 X 128

(V1MON) Battery WDO BATT-ON VOUT VOUT Data Sheet March 28, 2005

2 FN8133.0 March 28, 2005 A system battery switch circuit compares VCC (V1MON) with VBATT input and connects V OUT to whichever is higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X55060 can drive 50mA from V CC and 250µA from VBATT. The device switches to V BATT when V CC drops below the low VCC voltage threshold and VBATT > VCC. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC (V1MON) falls below the minimum VCC trip point (VTRIP1). RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply or monitors a second power supply voltage to provide a power fail warni ng. Intersil’s unique circuits allow the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision.

ORDERING INFORMATION

Suffix Vtrip1 Vtrip2 Temp Range V20-4.5A 4.6 2.6 0°C to 70°C V20I-4.5A -40°C to 85°C V20-4.5 4.6 2.9 0°C to 70°C V20I-4.5 -40°C to 85°C V20-2.7A 2.9 1.65 0°C to 70°C V20I-2.7A -40°C to 85°C V20-2.7 2.6 1.65 0°C to 70°C V20I-2.7 -40°C to 85°C 20-Pin TSSOP CS/WDI SO NC RESET/MR VCC (V1MON) BATT-ON VOUT5 RESET LOWLINE V2FAIL V2MON WP NC VSS VBATT SCK NC NC SI WDO X55060

3 FN8133.0 March 28, 2005 PIN DESCRIPTION Pin Name Function 1C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera- tion after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active.

2 NC No internal connections

3S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 4 RESET Reset Output. RESET is an active HIGH, open drain output which is the inverse of the RESET output. 5L O W L I N E Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1 and immediately goes HIGH when VCC > VTRIP1. This pin goes LOW 250ns before RESET pin. 6V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 7V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. 8W P Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits.

9 NC No internal connections

10 V SS Ground

11 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

12 NC No internal connections

13 NC No internal connections

14 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 15 V BATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri- mary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect VBATT to ground. X55060

4 FN8133.0 March 28, 2005 PRINCIPLES OF OPERATION Power-On Reset Application of power to the X55060 activates a Power- on Reset Circuit. This circuit goes active at about 1V and pulls the RESET /RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V CC exceeds the device VTRIP1 value for 150ms (nominal) the circuit releases RESET /RESET, allowing the proc essor to begin exe- cuting code. Low VCC (V1MON) Voltage Monitoring During operation, the X55060 monitors the V CC level and asserts RESET /RESET if supply voltage falls below a preset minimum V TRIP1. During this time the communication to the dev ice is interrupted. The RESET/RESET signal also pr events the microproces- sor from operating in a power fail or brownout condi- tion. The RESET signal remains active until the voltage drops below 1V. These also remain active until V CC returns and exceeds VTRIP1 for tPURST. Low V2MON Voltage Monitoring The X55060 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset mini- mum V TRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impend- ing power failure. V2FAIL remains active until V2MON returns and exceeds VTRIP2. The V2MON voltage sensor is powered by V OUT. If VCC and V BATT go away (i.e. V OUT goes away), then V2MON cannot be monitored. 16 V OUT Output Voltage. VOUT = VCC if VCC > VTRIP1. IF VCC < VTRIP1, then, VOUT = VCC if VCC > VBATT+0.03 VOUT = VBATT if VCC < VBATT-0.03 Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability. 17 BATT-ON Battery On. This open drain output goes HIGH when the VOUT switches to VBATT and goes LOW when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current requirements are greater than 50mA. The purpose of this output is to drive an external transistor to get higher operating currents when the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply enough voltage and current to keep SRAM devices from losing their data-there is no communication at this time.

18 RESET

/MR Output/Manual Reset Input. This is an Input/Output pin. RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. When RESET is active communication to the device is inter- rupted. RESET remains active until VCC rises above the minimum VCC sense level for 150ms. RESET also goes active on power-up and remains active for 150ms after the power supply stabilizes. MR Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins are asserted. When MR is released, the RESET/RESET remains asserted for tPURST, and then re- leased. 19 WDO Watchdog Output. WDO is an active low, open drain output which goes active whenever the watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.

20 V CC

(V1MON) Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1 voltage, RESET and RESET go ACTIVE. PIN DESCRIPTION (CONTINUED) Pin Name Function X55060

Figure 1. Two Uses of Dual Voltage Monitoring ting disables the watchdog timer. draw much less current than in their active mode. oscillations between supplies. circuits during normal operation. VCC > VTRIP1 Normal Operation. tion to the device is allowed.

and V2MON threshold (V TRIP1, V TRIP2) voltages. LOW to complete the operation. (desired) - VTRIPX (actual)). Figure 2. Example System Connection

LOW to complete the operation. Figure 3. Set VTRIPX Level Sequence Figure 4. Reset VTRIPX Level Sequence

16 Bits

col allowing operation on a simple four-wire bus. cycles and a minimum data retention of 100 years. with data being clocked in on the rising edge of SCK. must be LOW during the entire operation. completion of a valid Write Cycle. “0”, no write is in progress. Table 1. Instruction Set Note: *Instructions are shown MSB in leftmost pos ition. Instructions are transferred MSB first. Table 2. Block Protect Matrix

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

set HIGH and when WEL = 0 the latch is reset LOW. block lock protection of that portion of memory. programmed with the WRSR instruction. Note 1. Watchdog timer is shipped disabled. PURST time is set to 150ms at the factory. bits from inadvertent corruption. WP pin is LOW and the nonvolatile bit WPEN is “1”. ables subsequent write attempts to the Status Register. Figure 7. Read EEPROM Array Sequence

11 FN8133.0 March 28, 2005 When WP is HIGH, all function s, including nonvolatile writes to the Status Register operate normally. Setting the WPEN bit in the Status Register to “0” blocks the WP pin function, allowing writes to the Status Register when WP is HIGH or LOW. Setting the WPEN bit to “1” while the WP pin is LOW activates the Programma- ble ROM mode, thus requiring a change in the WP pin prior to subsequent Status Register changes. This allows manufacturing to in stall the device in a system with WP pin grounded and still be able to program the Status Register. Manufacturing can then load Configu- ration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the “OTP mode” by setting the WPEN bit. Data changes to protected areas of the device now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 7). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 8). Refer to the Serial Output Timing on page 18. Write Sequence Prior to any attempt to writ e data into th e device, the “Write Enable” Latch (WEL) must first be set by issu- ing the WREN instru ction (Figure 9). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are trans- mitted, CS must then be taken HIGH. If the user con- tinues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Opera- tion will be ignored. To write data to the EEPRO M memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the opera- tion. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 10). To write to the Status Regi ster, the WRSR instruction is followed by the data to be written (Figure 11). While the write is in progress following a Status Regis- ter or EEPROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. Refer to Serial Input timing on page 17. OPERATIONAL NOTES The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The Write Enable Latch is reset. – Reset Signal is active for t PURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A WREN instruction must be issued to set the Write Enable Latch. – A valid write command and address must be sent to the device. –C S must come HIGH after a multiple of 8 data bits in order to start a nonvolatile write cycle. X55060

14 FN8133.0 March 28, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with D.C. output current COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified. (VCC = 2.7V to 5.5V)) Symbol Parameter Limits Unit Test ConditionsMin. Typ. (5) Max. ICC1(1) VCC Supply Current (Active) (Excludes IOUT) Read Memory array (Excludes IOUT) Write nonvolatile Memory 1.5 3.0 mA SCK = V CC x 0.1/VCC x 0.9 @ 10MHz ICC2(2) VCC Supply Current (Passive) (Excludes IOUT) WDT on, 5V (Excludes IOUT) WDT on, 2.7V (Excludes IOUT) WDT off, 5V 50.0 40.0 30.0 90.0 60.0 50.0 µA CS = VCC, Any Input = VSS or VCC, VOUT, RESET, RESET, LOWLINE = Open ICC3(1) VCC Current (Battery Backup Mode) (Excludes IOUT) 1µ A V CC = 2V, VBATT = 2.8V, VOUT, RESET = Open IBATT1(3)(7 VBATT Current (Excludes IOUT)1 µ A V OUT = VBt IBATT2(7) VBATT Current (Excludes IOUT) (Battery Backup Mode) 0.4 1.0 µA V OUT = VBATT, VBATT =2 . 8 V VOUT, RESET = Open VOUT1(7) Output Voltage (VCC > VBATT + 0.03V or VCC > VTRIP1) VCC - 0.05 VCC - 0.5 VCC-0.02 VCC-0.2 V V IOUT = -5mA IOUT = -50mA VOUT2(7) Output Voltage (VCC < VBATT -0.03V and VCC < VTRIP1) {Battery Backup} VBATT - 0.2 V V IOUT = -250µA VOLB Output (BATT-ON) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) VBSH Battery Switch Hysteresis (VCC < VTRIP1) -30 mV mV Power-up Power-down RESET/RESET/LOWLINE/WDO 2.85 3.0 V -2.7A version 2.55 2.75 V -2.7 version V OLR Output (RESET, RESET, LOWLINE, WDO) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) X55060

15 FN8133.0 March 28, 2005 Notes: (1) The device enters the Active state after any start, and rema ins active until 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) Negative number indicate charging current, Positive numbers indicate discharge current. (4) V IL min. and VIH max. are for reference only and are not tested. (5) V CC = 5V at 25°C. (6) V TRIP1 and VTRIP2 are programmable. See page 22 and 23 for programming specifications and pages 6, 7 and 8 for programming pro- cedure. For custom programmed levels, contact factory. (7) Based on characterization data. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Note: (1) This parameter is periodically sampled and not 100% tested. Second Supply Monitor VTRIP2(6) V2MON Reset Trip Point Voltage 2.85 3.0 V -4.5 version 2.55 2.7 V -4.5A version 1.6 1.7 V -2.7A and -2.7 version VOLx Output (V2FAIL) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) SPI Interface VILx(4) Input (CS, SI, SCK, WP) LOW Voltage -0.5 V CC x 0.3 V VIHx(4) Input (CS, SI, SCK, WP) HIGH Voltage V CC x 0.7 V CC + 0.5 V ILIx Input Leakage Current (CS, SI, SCK,WP) ±10 µA VOLS Output (SO) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) VOHS Output (SO) HIGH Voltage V OUT - 0.8 V I OH = -1.0mA (5V) Symbol Test Max. Unit Conditions COUT(1) Output Capacitance (SO, RESET, V2FAIL, RESET, LOWLINE, BATT-ON,WDO)8 p FV OUT = 0V CIN(1) Input Capacitance (SCK, SI, CS, WP)6 p F V IN = 0V D.C. OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions unless otherwise specified. (VCC = 2.7V to 5.5V)) Symbol Parameter Limits Unit Test ConditionsMin. Typ. (5) Max. X55060

16 FN8133.0 March 28, 2005 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing VOUT SO 30pF RESET/RESET 2.06kΩ 3.03kΩ VOUT 1.53kΩ 30pF BATT-ON/LOWLINE/ V2FAIL, WDO Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 Symbol Parameter VCC = 2.7-5.5V UnitMin. Max. fSCK Clock Frequency 10 MHz tCYC Cycle Time 100 ns tLEAD CS Lead Time 50 ns tLAG CS Lag Time 200 ns tWH Clock HIGH Time 40 ns tWL Clock LOW Time 40 ns tSU Data Setup Time 10 ns tH Data Hold Time 10 ns tRI(3) Input Rise Time 20 ns tFI(3) Input Fall Time 20 ns tCS CS Deselect Time 50 ns tWC(4) Write Cycle Time 10 ms X55060

17 FN8133.0 March 28, 2005 Serial Input Timing Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock Frequency 10 MHz tDIS Output Disable Time 50 ns tV Output Valid from Clock Low 40 ns tHO Output Hold Time 0 ns tRO(3) Output Rise Time 25 ns tFO(3) Output Fall Time 25 ns SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance X55060

18 FN8133.0 March 28, 2005 Serial Output Timing Power-Up and Power-Down Timing SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG tVB1 RESET tVB2 tPURST tPURST tRPD VBATT VCC VBAT VOUT VOUT VTRIP1 VOUT VCC RESET BATT-ON X55060

19 FN8133.0 March 28, 2005 VCC to LOWLINE Timings V2MON to V2FAIL Timings RESET/RESET/LOWLINE Output Timing Notes: (1) This parameter is not 100% tested. (2) This measurement is from 10% to 90% of the supply voltage. (3) V CC = 5V at 25°C. (4) Based on characterization data only. Symbol Parameter Min. Typ. (3) Max. Unit tPURST RESET/RESET Time-out Period PUP = 0 PUP = 1 500 150 800 250 1200 ms tRPD(1) VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE 10 20 µs tRPD2(1) VTRIP2 to V2FAIL 10 20 µs tLR LOWLINE to RESET/RESET delay (Power-down only) 100 250 (4) 800 ns tF(2) VCC/V2MON Fall Time 1000 µs tR(2) VCC/V2MON Rise Time 1000 µs VRVALID Reset Valid VCC 1V tVB1 VBATT + 0.03 v to BATT-ON (logical 0) 20 (4) µs tVB2 VBATT - 0.03 v to BATT-ON (logical 1) 20 (4) µs VCC LOWLINE VTRIP VBATT VTRIP1 VOH VOL VTRIP1 tR tRPD tRPD tF VTRIP2 tR tRPD2 tRPD2 tF V2MON V2FAIL VOUT X55060

20 FN8133.0 March 28, 2005 CS/WDI vs. WDO Timing RESET/RESET Output Timing Notes: (1) V CC = 5V at 25°C. (2) Based on characterization data only. VTRIP Set/Reset Conditions Symbol Parameter Min. Typ. (1) Max. Unit tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 200 500 150 400 (2) 800(2) 250 600 1200 ms ms ms t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time Out 75 150 250 ms CS/WDI tCST WDO tWDO tRST tWDO tRST SCK CS * 0001h Set VTRIP102h VCC/V2MON WP tTHD tVPHtVPS VP VTRIPX tWC tVPO tPCS * 0003h Set VTRIP2 06h * 000Bh Reset VTRIP1 * 000Dh Reset VTRIP2 SI X = 1, 2 tTSU * all others reserved clocks X55060

21 FN8133.0 March 28, 2005 VTRIP1, VTRIP2 Programming Specifications VCC = 2.7-5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WP VTRIPX Program Voltage Setup time 10 µs tVPH WP VTRIPX Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 ms tWC VTRIPX Write Cycle Time 10 ms tVPO WP VTRIPX Program Voltage Off time before next cycle 1 ms VP Programming Voltage 10 15 V VTRAN VTRIPX Programed Voltage Range 2.5 5.0 V Vtv VTRIPX Program variation after programming (0–75°C). (Programmed at 25°C ac- cording to the procedure defined on pages 6, 7 and 8.) -25 +25 mV VTRIPX programming parameters are periodically sampled and are not 100% tested. X55060

22 FN8133.0 March 28, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X55060

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8133.0 March 28, 2005 Part Mark Information V20 = 20-Lead TSSOPWX55060 XYYww Date Code Part Mark VTRIP1 Range VTRIP2 Range Operating Temperature Range Part Number I -40°C-85°C X55060V20I-4.5A AM -40 °C-85°C X55060V20I-4.5 G- 4 0 °C-85°C X55060V20I-2.7A AP -40 °C-85°C X55060V20I-2.7 X55060