X5325S8Z-2.7A

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

Features

• Selectable watchdog timer
• L o w VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low V CC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a volatile flag bit
• Long battery life with low power consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock ™ protection - In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages - 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant) Block Diagram WATCHDOG TIMER RESET DATA REGISTER COMMAND DECODE AND CONTROL LOGIC SI SO SCK CS/WDI VCC RESET AND WATCHDOG TIMEBASE POWER-ON AND GENERATIONVTRIP RESET/RESET RESET LOW VOLTAGE STATUS REGISTER PROTECT LOGIC 8kBITS 8kBITS 16kBITS EEPROM ARRAY WATCHDOG TRANSITION DETECTOR WP X5323 = RESET X5325 = RESET VCC THRESHOLD RESET LOGIC

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 2 of 19 December 9, 2015

Ordering Information

(V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE RESET (Active Low) X5323PZ-4.5A (Note) (No longer available, recommended replacement: X5323S8Z-4.5A) X5323P ZAL 4.5 to 5.5 4.5 to 4.75 0 to +70 8 Ld PDIP (Pb-free) X5323PIZ-4.5A (Note) (No longer available, recommended replacement: X5323S8IZ-4.5A) X5323P ZAM -40 to +85 8 Ld PDIP (Pb-free) X5323S8Z-4.5A (Note) X5323 ZAL 0 to +70 8 Ld SOIC (Pb-free) X5323S8IZ-4.5A* (Note) X5323 ZAM -40 to +85 8 Ld SOIC (Pb-free) X5323V14-4.5A X5323 VAL 0 to +70 14 Ld TSSOP X5323PZ (Note) (No longer available, recommended replacement: X5323S8Z) X5323P Z 4.5 to 5.5 4.25 to 4.5 0 to +70 8 Ld PDIP (Pb-free) X5323PIZ (Note) (No longer available, recommended replacement: X5323S8IZ) X5323P ZI -40 to +85 8 Ld PDIP (Pb-free) X5323S8Z* (Note) X5323 Z 0 to +70 8 Ld SOIC (Pb-free) X5323S8IZ* (Note) X5323 ZI -40 to +85 8 Ld SOIC (Pb-free) X5323PZ-2.7A (Note) (No longer available, recommended replacement: X5323S8Z-2.7A) X5323P ZAN 2.7 to 5.5 2.85 to 3.0 0 to +70 8 Ld PDIP (Pb-free) X5323PIZ-2.7A (Note) (No longer available, recommended replacement: X5323S8IZ-2.7A) X5323P ZAP -40 to +85 8 Ld PDIP (Pb-free) X5323S8Z-2.7A* (Note) X5323 ZAN 0 to +70 8 Ld SOIC (Pb-free) X5323S8IZ-2.7A* (Note) X5323 ZAP -40 to +85 8 Ld SOIC (Pb-free) X5323PZ-2.7 (Note) (No longer available, recommended replacement: X5323S8Z-2.7) X5323P ZF 2.7 to 5.5 2.55 to 2.7 0 to +70 8 Ld PDIP (Pb-free) X5323PIZ-2.7 (Note) (No longer available, recommended replacement: X5323S8IZ-2.7) X5323P ZG -40 to +85 8 Ld PDIP (Pb-free) X5323S8Z-2.7* (Note) X5323 ZF 0 to +70 8 Ld SOIC (Pb-free) X5323S8IZ-2.7* (Note) X5323 ZG -40 to +85 8 Ld SOIC (Pb-free) RESET (Active High) X5325S8IZ-4.5A (Note) X5325 ZAM -40 to +85 8 Ld SOIC (Pb-free) X5325S8Z* (Note) X5325 Z 4.5 to 5.5 4.25 to 4.5 0 to +70 8 Ld SOIC (Pb-free) X5325S8IZ* (Note) X5325 ZI -40 to +85 8 Ld SOIC (Pb-free) X5325S8IZ-2.7A (Note) X5325 ZAP -40 to +85 8 Ld SOIC (Pb-free) X5325S8IZ-2.7* (Note) X5325 ZG -40 to +85 8 Ld SOIC (Pb-free) *Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 3 of 19 December 9, 2015 Pinouts X5323, X5325 (8 LD SOIC, PDIP) TOP VIEW X5323, X5325 (14 LD TSSOP) TOP VIEW CS/WDI WP SO RESET/RESET VCC VSS SCK SI SO WP VSS SCK SI NC V CC NC CS/WDI NC NC NC NC RESET/RESET Pin Descriptions PIN NUMBER (SOIC/PDIP) PIN NUMBER TSSOP PIN NAME PIN FUNCTION 11 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 36 W P Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits.

47 V SS Ground

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power- up at about 1V and remains active for 200ms after the power supply stabilizes. 3 to 5,10 to 12 NC No internal connections

minimum data retention of 100 years. condition and after the completion of a valid write cycle. The RDSR instruction provides access to the status register. and can be reset by the WRDS instruction. protection of that portion of memory. NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 1. INSTRUCTION SET TABLE 2. BLOCK PROTECT MATRIX

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

instructions. The flag bit is automatically reset upon power-up. = 1. The factory default for Memory Block Protection is ‘None’. from inadvertent corruption. nonvolatile writes to the device’s status register. attempts to the status register. grounded and still be able to program the status register. changes now require a hardware change. memory at the selected address is shifted out on the SO line. FIGURE 5. READ EEPROM ARRAY SEQUENCE

read EEPROM Array Sequence (Figure 1). other time, the write operation will not be completed (Figure 4). the WIP bit. During this time the WIP bit will be high.

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for t PURST. Data Protection The following circuitry has been included to prevent inadvertent writes:
• A WREN instruction must be issued to set the write enable latch.
• C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle. 0123456789 1 0 1 1 1 2 1 3 1 4 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION

FIGURE 6. READ STATUS REGISTER SEQUENCE

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 10 of 19 December 9, 2015 Absolute Maximum Ratings Thermal Information Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCC Write Current (active) I CC1 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 5 mA VCC Read Current (active) I CC2 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 0.4 mA VCC Standby Current WDT = OFF I SB1 CS = VCC, VIN = VSS or VCC, VCC =5 . 5 V 1 µ A VCC Standby Current WDT = ON I SB2 CS = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA VCC Standby Current WDT = ON I SB3 CS = VCC, VIN = VSS or VCC, VCC =3.6V 20 µA Input Leakage Current I LI VIN = VSS to VCC 0 . 1 1 0 µ A Output Leakage Current I LO VOUT = VSS to VCC 0.1 10 µA Input LOW Voltage V IL (Note 1) -0.5 V CC x 0.3 V Input HIGH Voltage V IH (Note 1) VCC x 0.7 V CC + 0.5 V Output LOW Voltage V OL1 VCC > 3.3V, IOL = 2.1mA 0.4 V Output LOW Voltage V OL2 2V < VCC  3.3V, IOL = 1mA 0.4 V Output LOW Voltage V OL3 VCC  2V, IOL = 0.5mA 0.4 V Output HIGH Voltage V OH1 VCC > 3.3V, IOH = -1.0mA V CC - 0.8 V Output HIGH Voltage V OH2 2V < VCC  3.3V, IOH = -0.4mA V CC - 0.4 V Output HIGH Voltage V OH3 VCC 2V, IOH = -0.25mA V CC - 0.2 V Reset Output LOW Voltage V OLS IOL = 1mA 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST CONDITIONS MAX UNIT COUT (Note 2) Output Capacitance (SO, RESET /RESET) V OUT = 0V 8 pF CIN (Note 2) Input Capacitance (SCK, SI, CS , WP)V IN = 0V 6 pF NOTES: 1. VIL min and VIH max are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 11 of 19 December 9, 2015 Equivalent AC Load Circuit at 5V VCC Serial Input Timing OUTPUT 100pF 4.6k RESET/RESET 30pF 2.06k 3.03k AC Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 level = VCC x 0.5. Over recommended operating conditions, unless otherwise specified. PARAMETER SYMBOL 2.7 TO 5.5V UNITMIN MAX SERIAL INPUT TIMING Clock Frequency f SCK 02M H z Cycle Time t CYC 500 ns CS Lead Time t LEAD 250 ns CS Lag Time t LAG 250 ns Clock HIGH Time t WH 200 ns Clock LOW Time t WL 250 ns Data Set-up Time t SU 50 ns Data Hold Time t H 50 ns Input Rise Time t RI (Note 3) 100 ns Input Fall Time t FI (Note 3) 100 ns CS Deselect Time t CS 500 ns Write Cycle Time t WC (Note 4) 10 ms SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI HIGH IMPEDANCE

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 12 of 19 December 9, 2015 Serial Output Timing Power-Up and Power-Down Timing Serial Output Timing PARAMETER SYMBOL 2.7 TO 5.5V UNITMIN MAX Clock Frequency f SCK 02 M H z Output Disable Time t DIS 250 ns Output Valid From Clock Low t V 250 ns Output Hold Time t HO 0n s Output Rise Time t RO (Note 3) 100 ns Output Fall Time t FO (Note 3) 100 ns NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. SCK CS SO SI MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG RESET (X5323) RESET (X5323) VCC tPURST tPURST tR tF tRPD VTRIP VTRIP

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 13 of 19 December 9, 2015 CS/WDI vs RESET/RESET Timing RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT Reset Trip Point Voltage, X5323, X5325 4.25 4.38 4.5 V V TH VTRIP Hysteresis (HIGH to LOW vs LOW to HIGH VTRIP Voltage) 20 mV tPURST Power-up Reset Time-Out 100 200 280 ms tRPD (Note 5) V CC Detect To Reset/Output 500 ns tF (Note 5) V CC Fall Time 100 µs tR (Note 5) V CC Rise Time 100 µs VRVALID Reset Valid VCC 1V NOTE: 5. This parameter is periodically sampled and not 100% tested. CS/WDI tCST RESET tWDO tRST tWDO tRST RESET RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog Time-Out Period WD1 = 1, WD0 = 0 100 200 300 ms WD1 = 0, WD0 = 1 450 600 800 ms WD1 = 0, WD0 = 0 1 1.4 2 s t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time-Out 100 200 300 ms

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 14 of 19 December 9, 2015 VTRIP Set Conditions VTRIP Reset Conditions SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC* *VCC > PROGRAMMED VTRIP VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP Program Voltage Set-up Time 1 µs tVPH SCK VTRIP Program Voltage Hold Time 1 µs tP VTRIP Program Pulse Width 1µ s tTSU VTRIP Level Set-up Time 10 µs tTHD VTRIP Level Hold (Stable) Time 10 ms

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 16 of 19 December 9, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FIGURE 14. TPURST vs TEMPERATURE FIGURE 15. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 9, 2015 FN8131.3 Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections. Replaced POD MDP0027 with M8.15E

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 17 of 19 December 9, 2015 Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 Page 18 of 19 December 9, 2015 Package Outline Drawing M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09 Unless otherwise specified, tolerance : Decimal ± 0.05 The pin #1 identifier may be either a mold or mark feature. Interlead flash or protrusions shall not exceed 0.25mm per side. Dimension does not include interlead flash or protrusions. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Dimensions are in millimeters.1. NOTES: DETAIL "A" SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN TOP VIEW A B

0.25 AMC B

C 0.10 C ID MARK PIN NO.1 (0.35) x 45° SEATING PLANE GAUGE PLANE 0.25 (5.40) (1.50) 4.90 ± 0.10 3.90 ± 0.10 1.27 0.43 ± 0.076 0.63 ±0.23 4° ± 4° DETAIL "A" 0.22 ± 0.03 0.175 ± 0.075 1.45 ± 0.1

1.75 MAX

(1.27) (0.60) 6.0 ± 0.20 Reference to JEDEC MS-012.6. SIDE VIEW “B”

FN8131 Rev 3.00 Page 19 of 19 December 9, 2015 X5323, X5325 (Replaces X25323, X25325) Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7  0o 8o 0o 8o - Rev. 2 4/06