X5323S8Z-2.7A

X5323S8IZT1 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 20

Technical content

Features

• Selectable watchdog timer
• L o w VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low V CC reset threshold voltage using special programming sequence - Reset signal valid to V CC = 1V
• Determine watchdog or low voltage reset with a volatile flag bit
• Long battery life with low power consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or al l of EEPROM array with Block Lock ™ protection - In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages - 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant) Block Diagram WATCHDOG TIMER RESET DATA REGISTER COMMAND DECODE AND CONTROL LOGIC SI SO SCK CS/WDI VCC RESET AND WATCHDOG TIMEBASE POWER-ON AND GENERATIONVTRIP RESET/RESET RESET LOW VOLTAGE STATUS REGISTER PROTECT LOGIC 8kBITS 8kBITS 16kBITS EEPROM ARRAY WATCHDOG TRANSITION DETECTOR WP X5323 = RESET X5325 = RESET VCC THRESHOLD RESET LOGIC Data Sheet June 30, 2008

2 FN8131.2 June 30, 2008

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE X5323PZ-4.5A (Note) X5323P ZAL X5325PZ-4.5A X5325P ZAL 0 to +70 8 Ld PDIP (Pb-free) X5323PI-4.5A X5323P AM X5325PI-4.5A X5325P AM -40 to +85 8 Ld PDIP X5323PIZ-4.5A (Note) X5323P ZAM X5325PIZ-4.5A X5325P ZAM -40 to +85 8 Ld PDIP (Pb-free) X5323S8-4.5A X5323 AL X5325S8-4.5A X5325 AL 0 to +70 8 Ld SOIC X5323S8Z-4.5A (Note) X5323 ZAL X5325S8Z-4.5A (Note) X5325 ZAL 0 to +70 8 Ld SOIC (Pb-free) X5323S8I-4.5A* X5323 AM X5325S8I-4.5A X5325 AM -40 to +85 8 Ld SOIC X5323S8IZ-4.5A* (Note) X5323 ZAM X5325S8IZ-4.5A (Note) X5325 ZAM -40 to +85 8 Ld SOIC (Pb-free) X5323V14-4.5A X5323 VAL X5325V14-4.5A X5325 VAL 0 to +70 14 Ld TSSOP X5323V14Z-4.5A (Note) X5323 VZAL X5325V14Z-4.5A (Note) X5325 VZAL 0 to +70 14 Ld TSSOP (Pb-free) X5323V14I-4.5A X5323 VAM X5325V14I-4.5A X5325 VAM -40 to +85 14 Ld TSSOP X5323V14IZ-4.5A (Note) X5323 VZAM X5325V14IZ-4.5A (Note) X5325 VZAM -40 to +85 14 Ld TSSOP (Pb-free) X5323P X5323P X5325P X5325P 4.5 to 5.5 4.25 to 4.5 0 to +70 8 Ld PDIP X5323PZ (Note) X5323P Z X5325PZ X5325P Z 0 to +70 8 Ld PDIP (Pb-free) X5323PI X5323P I X5325PI X5325P I -40 to +85 8 Ld PDIP X5323PIZ (Note) X5323P ZI X5325PIZ X5325P ZI -40 to +85 8 Ld PDIP (Pb-free) X5323S8* X5323 X5325S8* X5325 0 to +70 8 Ld SOIC X5323S8Z* (Note) X5323 Z X5325S8Z* (Note) X5325 Z 0 to +70 8 Ld SOIC (Pb-free) X5323S8I* X5323 I X5325S8I* X5325 I -40 to +85 8 Ld SOIC X5323S8IZ* (Note) X5323 ZI X5325S8IZ* (Note) X5325 ZI -40 to +85 8 Ld SOIC (Pb-free) X5323V14* X5323 V X5325V14* X5325 V 0 to +70 14 Ld TSSOP X5323V14Z* (Note) X5323 VZ X5325V14Z* (Note) X5325 VZ 0 to +70 14 Ld TSSOP (Pb-free) X5323V14I* X5323 VI X5325V14I* X5325 VI -40 to +85 14 Ld TSSOP X5323V14IZ* (Note) X5323 VZI X5325V14IZ* (Note) X5325 VZI -40 to +85 14 Ld TSSOP (Pb-free) X5323PZ-2.7A (Note) X5323P ZAN X5325PZ-2.7A X5325P ZAN 0 to +70 8 Ld PDIP (Pb-free) X5323PI-2.7A X5323P AP X5325PI-2.7A X5325P AP -40 to +85 8 Ld PDIP X5323PIZ-2.7A (Note) X5323P ZAP X5325PIZ-2.7A X5325P ZAP -40 to +85 8 Ld PDIP (Pb-free) X5323S8-2.7A* X5323 AN X5325S8-2.7A X5325 AN 0 to +70 8 Ld SOIC X5323S8Z-2.7A* (Note) X5323 ZAN X5325S8Z-2.7A (Note) X5325 ZAN 0 to +70 8 Ld SOIC (Pb-free) X5323S8I-2.7A* X5323 AP X5325S8I-2.7A X5325 AP -40 to +85 8 Ld SOIC X5323S8IZ-2.7A* (Note) X5323 ZAP X5325S8IZ-2.7A (Note) X5325 ZAP -40 to +85 8 Ld SOIC (Pb-free) X5323, X5325

3 FN8131.2 June 30, 2008 X5323V14Z-2.7A (Note) X5323 VZAN X5325V14Z-2.7A (Note) X5325 VZAN 0 to +70 14 Ld TSSOP (Pb-free) X5323V14I-2.7A X5323 VAP X5325V14I-2.7A X5325 VAP -40 to +85 14 Ld TSSOP X5323V14IZ-2.7A (Note) X5323 VZAP X5325V14IZ-2.7A (Note) X5325 VZAP -40 to +85 14 Ld TSSOP (Pb-free) X5323PZ-2.7 (Note) X5323P ZF X5325PZ-2.7 X5325P ZF 0 to +70 8 Ld PDIP (Pb-free) X5323PI-2.7 X5323P G X5325PI-2.7 X5325P G -40 to +85 8 Ld PDIP X5323PIZ-2.7 (Note) X5323P ZG X5325PIZ-2.7 X5325P ZG -40 to +85 8 Ld PDIP (Pb-free) X5323S8-2.7* X5323 F X5325S8-2.7* X5325 F 0 to +70 8 Ld SOIC X5323S8Z-2.7* (Note) X5323 ZF X5325S8Z-2.7* (Note) X5325 ZF 0 to +70 8 Ld SOIC (Pb-free) X5323S8I-2.7* X5323 G X5325S8I-2.7* X5325 G -40 to +85 8 Ld SOIC X5323S8IZ-2.7* (Note) X5323 ZG X5325S8IZ-2.7* (Note) X5325 ZG -40 to +85 8 Ld SOIC (Pb-free) X5323V14-2.7* X5323 VF X5325V14-2.7* X5325 VF 0 to +70 14 Ld TSSOP X5323V14Z-2.7* (Note) X5323 VZF X5325V14Z-2.7* (Note) X5325 VZF 0 to +70 14 Ld TSSOP (Pb-free) X5323V14I-2.7* X5323 VG X5325V14I-2.7* X5325 VG -40 to +85 14 Ld TSSOP X5323V14IZ-2.7* (Note) X5323 VZG X5325V14IZ-2.7* (Note) X5325 VZG -40 to +85 14 Ld TSSOP (Pb-free) *Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE Pinouts X5323, X5325 (8 LD SOIC, PDIP) TOP VIEW X5323, X5325 (14 LD TSSOP) TOP VIEW CS/WDI WP SO RESET/RESET VCC VSS SCK SI SO WP VSS SCK SI NC V CC NC CS/WDI NC NC NC NC RESET/RESET X5323, X5325

4 FN8131.2 June 30, 2008 Pin Descriptions PIN NUMBER (SOIC/PDIP) PIN NUMBER TSSOP PIN NAME PIN FUNCTION 11 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

36 W P

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits.

47 V SS Ground

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power- up at about 1V and remains active for 200ms after the power supply stabilizes. 3 to 5,10 to 12 NC No internal connections X5323, X5325

operation on a simple four-wire bus. minimum data retention of 100 years. LOW during the entire operation. The RDSR instruction provides access to the status register. instruction and can be reset by the WRDS instruction. block lock protection of that portion of memory. NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 1. INSTRUCTION SET TABLE 2. BLOCK PROTECT MATRIX

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

programmed with the WRSR instruction. from inadvertent corruption. nonvolatile writes to the device’s status register. subsequent write attempts to the status register. transmitted to the device, followed by the 16-bit address. the next higher address after each byte of data is shifted out. FIGURE 5. READ EEPROM ARRAY SEQUENCE

select the device followed by the 8-bit RDSR instruction. status register sequence (Figure 2). have been previously written. check the WIP bit. During this time the WIP bit will be high.

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for t PURST. Data Protection The following circuitry has been included to prevent inadvertent writes:
• A WREN instruction must be issued to set the write enable latch.
• C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle. 0123456789 1 0 1 1 1 2 1 3 1 4 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION

FIGURE 6. READ STATUS REGISTER SEQUENCE

11 FN8131.2 June 30, 2008 Absolute Maximum Ratings Thermal Information Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCC Write Current (active) I CC1 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 5 mA VCC Read Current (active) I CC2 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 0.4 mA VCC Standby Current WDT = OFF I SB1 CS = VCC, VIN = VSS or VCC, VCC =5 . 5 V 1 µ A VCC Standby Current WDT = ON I SB2 CS = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA VCC Standby Current WDT = ON I SB3 CS = VCC, VIN = VSS or VCC, VCC =3.6V 20 µA Input Leakage Current I LI VIN = VSS to VCC 0.1 10 µA Output Leakage Current I LO VOUT = VSS to VCC 0.1 10 µA Input LOW Voltage V IL (Note 1) -0.5 V CC x 0.3 V Input HIGH Voltage V IH (Note 1) VCC x 0.7 V CC + 0.5 V Output LOW Voltage V OL1 VCC > 3.3V, IOL = 2.1mA 0.4 V Output LOW Voltage V OL2 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V Output LOW Voltage V OL3 VCC ≤ 2V, IOL = 0.5mA 0.4 V Output HIGH Voltage V OH1 VCC > 3.3V, IOH = -1.0mA V CC - 0.8 V Output HIGH Voltage V OH2 2V < VCC ≤ 3.3V, IOH = -0.4mA V CC - 0.4 V Output HIGH Voltage V OH3 VCC ≤ 2V, IOH = -0.25mA V CC - 0.2 V Reset Output LOW Voltage V OLS IOL = 1mA 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST CONDITIONS MAX UNIT COUT (Note 2) Output Capacitance (SO, RESET /RESET) V OUT = 0V 8 pF CIN (Note 2) Input Capacitance (SCK, SI, CS , WP)V IN = 0V 6 pF NOTES: 1. V IL min and VIH max are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. X5323, X5325

12 FN8131.2 June 30, 2008 Equivalent AC Load Circuit at 5V VCC Serial Input Timing OUTPUT 100pF 4.6kΩ RESET/RESET 30pF 2.06kΩ 3.03kΩ AC Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 level = VCC x 0.5. Over recommended operating conditions, unless otherwise specified. PARAMETER SYMBOL 2.7 TO 5.5V UNITMIN MAX SERIAL INPUT TIMING Clock Frequency f SCK 02M H z Cycle Time t CYC 500 ns CS Lead Time t LEAD 250 ns CS Lag Time t LAG 250 ns Clock HIGH Time t WH 200 ns Clock LOW Time t WL 250 ns Data Set-up Time t SU 50 ns Data Hold Time t H 50 ns Input Rise Time t RI (Note 3) 100 ns Input Fall Time t FI (Note 3) 100 ns CS Deselect Time t CS 500 ns Write Cycle Time t WC (Note 4) 10 ms SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI HIGH IMPEDANCE X5323, X5325

13 FN8131.2 June 30, 2008 Serial Output Timing Power-Up and Power-Down Timing Serial Output Timing PARAMETER SYMBOL 2.7 TO 5.5V UNITMIN MAX Clock Frequency f SCK 02 M H z Output Disable Time t DIS 250 ns Output Valid From Clock Low t V 250 ns Output Hold Time t HO 0n s Output Rise Time t RO (Note 3) 100 ns Output Fall Time t FO (Note 3) 100 ns NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. SCK CS SO SI MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG RESET (X5323) RESET (X5323) VCC tPURST tPURST tR tF tRPD VTRIP VTRIP X5323, X5325

14 FN8131.2 June 30, 2008 CS/WDI vs RESET/RESET Timing RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT Reset Trip Point Voltage, X5323, X5325 4.25 4.38 4.5 V V TH VTRIP Hysteresis (HIGH to LOW vs LOW to HIGH VTRIP Voltage) 20 mV tPURST Power-up Reset Time-Out 100 200 280 ms tRPD (Note 5) V CC Detect To Reset/Output 500 ns tF (Note 5) V CC Fall Time 100 µs tR (Note 5) V CC Rise Time 100 µs VRVALID Reset Valid VCC 1V NOTE: 5. This parameter is periodically sampled and not 100% tested. CS/WDI tCST RESET tWDO tRST tWDO tRST RESET RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog Time-Out Period WD1 = 1, WD0 = 0 100 200 300 ms WD1 = 0, WD0 = 1 450 600 800 ms WD1 = 0, WD0 = 0 1 1.4 2 s t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time-Out 100 200 300 ms X5323, X5325

15 FN8131.2 June 30, 2008 VTRIP Set Conditions VTRIP Reset Conditions SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC* *VCC > PROGRAMMED VTRIP VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP Program Voltage Set-up Time 1 µs tVPH SCK VTRIP Program Voltage Hold Time 1 µs tP VTRIP Program Pulse Width 1µ s tTSU VTRIP Level Set-up Time 10 µs tTHD VTRIP Level Hold (Stable) Time 10 ms X5323, X5325

FIGURE 14. TPURST vs TEMPERATURE FIGURE 15. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)

18 FN8131.2 June 30, 2008 X5323, X5325 Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

19 FN8131.2 June 30, 2008 X5323, X5325 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8131.2 June 30, 2008 X5323, X5325 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06