X5323P

X5323 INTERSIL | Alldatasheet

Document overview

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Technical content

FN8131.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X5323, X5325 (Replaces X25323, X25325) CPU Supervisor with 32Kb SPI EEPROM

FEATURES

• Selectable watchdog timer
• L o w VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
• Determine watchdog or low voltage reset with a volatile flag bit
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock ™ protection —In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages —14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Five industry stan- dard V TRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP RESET/RESET Reset Low Voltage Status Register Protect Logic 8Kbits 8Kbits 16Kbits EEPROM Array Watchdog Transition Detector WP X5323 = RESET X5325 = RESET VCC Threshold Reset Logic Data Sheet October 27, 2005

2 FN8131.1 October 27, 2005

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKNIG VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE X5323PZ-4.5A (Note) X5323P Z AL X5325PZ-4.5A X5325P Z AL 0 to 70 8 Ld PDIP (Pb-free) X5323PI-4.5A X5323P AM X5325PI-4.5A X5325P AM -40 to 85 8 Ld PDIP X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A X5325P Z AM -40 to 85 8 Ld PDIP (Pb-free) X5323S8-4.5A X5323 AL X5325S8-4.5A X5325 AL 0 to 70 8 Ld SOIC X5323S8Z-4.5A (Note) X5323 Z AL X5325S8Z-4.5A (Note) X5325 Z AL 0 to 70 8 Ld SOIC (Pb-free) X5323S8I-4.5A* X5323 AM X5325S8I-4.5A X5325 AM -40 to 85 8 Ld SOIC X5323S8IZ-4.5A* (Note) X5323 Z AM X5325S8IZ-4.5A (Note) X5325 Z AM -40 to 85 8 Ld SOIC (Pb-free) X5323V14-4.5A X5325V14-4.5A 0 to 70 14 Ld TSSOP X5323V14Z-4.5A (Note) X5323V Z AL X5325V14Z-4.5A (Note) X5325V Z AL 0 to 70 14 Ld TSSOP (Pb-free) X5323V14I-4.5A X5325V14I-4.5A -40 to 85 14 Ld TSSOP X5323V14IZ-4.5A (Note) X5323V Z AM X5325V14IZ-4.5A (Note) X5325V Z AM -40 to 85 14 Ld TSSOP (Pb-free) X5323P X5323P X5325P X5325P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP X5323PZ (Note) X5323P Z X5325PZ X5325P Z 0 to 70 8 Ld PDIP (Pb-free) X5323PI X5323P I X5325PI X5325P I -40 to 85 8 Ld PDIP X5323PIZ (Note) X5323P Z I X5325PIZ X5325P Z I -40 to 85 8 Ld PDIP (Pb-free) X5323S8* X5323 X5325S8* X5325 0 to 70 8 Ld SOIC X5323S8Z* (Note) X5323 Z X5325S8Z* (Note) X5325 Z 0 to 70 8 Ld SOIC (Pb-free) X5323S8I* X5323 I X5325S8I* X5325 I -40 to 85 8 Ld SOIC X5323S8IZ* (Note) X5323 Z I X5325S8IZ* (Note) X5325 Z I -40 to 85 8 Ld SOIC (Pb-free) X5323V14* X5323V X5325V14* 0 to 70 14 Ld TSSOP X5323V14Z* (Note) X5323V Z X5325V14Z* (Note) X5325V Z 0 to 70 14 Ld TSSOP (Pb-free) X5323V14I* X5325V14I* -40 to 85 14 Ld TSSOP X5323V14IZ* (Note) X5323V Z I X5325V14IZ* (Note) X5325V Z I -40 to 85 14 Ld TSSOP (Pb-free) X5323PZ-2.7A (Note) X5323P Z AN X5325PZ-2.7A X5325P Z AN 0 to 70 8 Ld PDIP (Pb-free) X5323PI-2.7A X5323P AP X5325PI-2.7A X5325P AP -40 to 85 8 Ld PDIP X5323PIZ-2.7A (Note) X5323P Z AP X5325PIZ-2.7A X5325P Z AP -40 to 85 8 Ld PDIP (Pb-free) X5323S8-2.7A* X5323 AN X5325S8-2.7A X5325 AN 0 to 70 8 Ld SOIC X5323S8Z-2.7A* (Note) X5323 Z AN X5325S8Z-2.7A (Note) X5325 Z AN 0 to 70 8 Ld SOIC (Pb-free) X5323S8I-2.7A* X5323 AP X5325S8I-2.7A X5325 AP -40 to 85 8 Ld SOIC X5323S8IZ-2.7A* (Note) X5323 Z AP X5325S8IZ-2.7A (Note) X5325 Z AP -40 to 85 8 Ld SOIC (Pb-free) X5323, X5325

3 FN8131.1 October 27, 2005 X5323V14Z-2.7A (Note) X5323V Z AN X5325V14Z-2.7A (Note) X5325V Z AN 0 to 70 14 Ld TSSOP (Pb-free) X5323V14I-2.7A X5325V14I-2.7A -40 to 85 14 Ld TSSOP X5323V14IZ-2.7A (Note) X5323V Z AP X5325V14IZ-2.7A (Note) X5325V Z AP -40 to 85 14 Ld TSSOP (Pb-free) X5323PZ-2.7 (Note) X5323P Z F X5325PZ-2.7 X5325P Z F 0 to 70 8 Ld PDIP (Pb-free) X5323PI-2.7 X5323P G X5325PI-2.7 X5325P G -40 to 85 8 Ld PDIP X5323PIZ-2.7 (Note) X5323P Z G X5325PIZ-2.7 X5325P Z G -40 to 85 8 Ld PDIP (Pb-free) X5323S8-2.7* X5323 F X5325S8-2.7* X5325 F 0 to 70 8 Ld SOIC X5323S8Z-2.7* (Note) X5323 Z F X5325S8Z-2.7* (Note) X5325 Z F 0 to 70 8 Ld SOIC (Pb-free) X5323S8I-2.7* X5323 G X5325S8I-2.7* X5325 G -40 to 85 8 Ld SOIC X5323S8IZ-2.7* (Note) X5323 Z G X5325S8IZ-2.7* (Note) X5325 Z G -40 to 85 8 Ld SOIC (Pb-free) X5323V14-2.7* X5325V14-2.7* X5325V F 0 to 70 14 Ld TSSOP X5323V14Z-2.7* (Note) X5323V Z F X5325V14Z-2.7* (Note) X5325V Z F 0 to 70 14 Ld TSSOP (Pb-free) X5323V14I-2.7* X5325V14I-2.7* -40 to 85 14 Ld TSSOP X5323V14IZ-2.7* (Note) X5323V Z G X5325V14IZ-2.7* (Note) X5325V Z G -40 to 85 14 Ld TSSOP (Pb-free) *Add "-T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKNIG VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE X5323, X5325

4 FN8131.1 October 27, 2005 PIN CONFIGURATION PIN DESCRIPTION Pin (SOIC/PDIP) Pin TSSOP Name Function 11 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch- dog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

36 W P

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits.

47 V SS Ground

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will re- main active until VCC rises above the minimum VCC sense level for 200ms. RE- SET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-up at about 1V and remains active for 200ms after the power supply stabilizes. 3-5,10-12 NC No internal connections X5323/25 X5323/25

8 Ld SOIC/PDIP

14 Ld TSSOP

V CC NC VSS SCK SI CS/WDT NC NC NC NC RESET/RESET X5323, X5325

col allowing operation on a simple four-wire bus. cycles and a minimum data retention of 100 years. with data being clocked in on the rising edge of SCK. must be LOW during the entire operation. it again to resume operations where left off. after the completion of a valid write cycle. “0”, no write is in progress. Table 1. Instruction Set Note: *Instructions are shown MSB in leftmost pos ition. Instructions are transferred MSB first. Table 2. Block Protect Matrix

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

one quarter, one half, all or none of the EEPROM array. programmed with the WRSR instruction. result of a watchdog time out or power failure.

1. The factory default for Memory Block Protection is

Figure 5. Read EEPROM Array Sequence

9 FN8131.1 October 27, 2005 In Circuit Programmable ROM Mode This mechanism protects the block lock and watchdog bits from inadvertent corruption. In the locked state (programmable ROM mode) the WP pin is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s status register. Setting the WP pin LOW while WPEN is a “1” while an internal write cycle to the status register is in progress will not stop this write operation, but the operation dis- ables subsequent write attempts to the status register. When WP is HIGH, all function s, including nonvolatile writes to the status register operate normally. Setting the WPEN bit in the status register to “0” blocks the WP pin function, allowing writes to the status register when WP is HIGH or LOW. Setting the WPEN bit to “1” while the WP pin is LOW activates the programma- ble ROM mode, thus requiring a change in the WP pin prior to subsequent status register changes. This allows manufacturing to in stall the device in a system with WP pin grounded and still be able to program the status register. Manufacturing can then load configura- tion data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the “OTP mode” by setting the WPEN bit. Data changes now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequen- tially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM Array Sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruc- tion. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPRO M memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the opera- tion. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be “0”. While the write is in progress following a status regis- ter or EEPROM Sequence, th e status register may be read to check the WIP bit. During this time the WIP bit will be high. OPERATIONAL NOTES The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The write enable latch is reset. – The flag bit is reset. – Reset signal is active for t PURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A WREN instruction must be issued to set the write enable latch. –C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle. X5323, X5325

Figure 9. Status Register Write Sequence

12 FN8131.1 October 27, 2005 ABSOLUTE MAXIMUM RATINGS COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) CAPACITANCE T A = +25°C, f = 1MHz, VCC = 5V Notes: (1) V IL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Unit Test ConditionsMin. Typ. Max. ICC1 VCC write current (active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ICC2 VCC read current (active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ISB1 VCC standby current WDT = OFF 1µ A C S = VCC, VIN = VSS or VCC, VCC =5 . 5 V ISB2 VCC standby current WDT = ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC standby current WDT = ON 20 µA CS = VCC, VIN = VSS or VCC, VCC =3.6V ILI Input leakage current 0.1 10 µA V IN = VSS to VCC ILO Output leakage current 0.1 10 µA V OUT = VSS to VCC VIL(1) Input LOW voltage -0.5 V CC x 0.3 V VIH(1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < V CC ≤ 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V V CC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH voltage V CC - 0.8 V V CC > 3.3V, IOH = -1.0mA VOH2 Output HIGH voltage V CC - 0.4 V 2V < V CC ≤ 3.3V, IOH = -0.4mA VOH3 Output HIGH voltage V CC - 0.2 V V CC ≤ 2V, IOH = -0.25mA VOLS Reset output LOW voltage 0.4 V I OL = 1mA Symbol Test Max. Unit Conditions COUT(2) Output capacitance (SO, RESET/RESET) 8 pF V OUT = 0V CIN(2) Input capacitance (SCK, SI, CS, WP)6 p F V IN = 0V RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Device Option Supply Voltage -2.7 or -2.7A 2.7V to 5.5V Blank or -4.5A 4.5V-5.5V X5323, X5325

13 FN8131.1 October 27, 2005 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing Output 100pF 4.6kΩ RESET/RESET 30pF 2.06kΩ 3.03kΩ Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 Symbol Parameter 2.7–5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 250 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) Input rise time 100 ns tFI(3) Input fall time 100 ns tCS CS deselect time 500 ns tWC(4) Write cycle time 10 ms X5323, X5325

14 FN8131.1 October 27, 2005 Serial Input Timing Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock frequency 0 2 MHz tDIS Output disable time 250 ns tV Output valid from clock low 250 ns tHO Output hold time 0 ns tRO(3) Output rise time 100 ns tFO(3) Output fall time 100 ns SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG X5323, X5325

15 FN8131.1 October 27, 2005 Power-Up and Power-Down Timing RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5323-4.5A, X5323-4.5A Reset trip point voltage, X5323, X5325 Reset trip point voltage, X5323-2.7A, X5325-2.7A Reset trip point voltage, X5323-2.7, X5325-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.92 2.63 4.75 4.5 3.0 2.7 V V TH VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV tPURST Power-up reset time out 100 200 280 ms tRPD(5) VCC detect to reset/output 500 ns tF(5) VCC fall time 100 µs tR(5) VCC rise time 100 µs VRVALID Reset valid VCC 1V RESET (X5323) RESET (X5323) VCC tPURST tPURST tR tF tRPD

0 Volts

X5323, X5325

16 FN8131.1 October 27, 2005 RESET/RESET Output Timing VTRIP Set Conditions VTRIP Reset Conditions Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec tCST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 300 ms SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC* *VCC > Programmed VTRIP X5323, X5325

17 FN8131.1 October 27, 2005 VTRIP Programming Specifications VCC = 1.7–5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK VTRIP program voltage setup time 1 µs tVPH SCK VTRIP program voltage hold time 1 µs tP VTRIP program pulse width 1 µs tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms tVPO SCK VTRIP program voltage off time before next cycle 0 ms VP Programming voltage 15 18 V VTRAN VTRIP programed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) -25 +25 mV Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP program variation after programming (0–75°C). (programmed at 25°C) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. X5323, X5325

18 FN8131.1 October 27, 2005 TYPICAL PERFORMANCE Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer Off (VCC= 3V, 5V) -40 25 90 Temp (°C) Isb (µA) VCC Supply Current vs. Temperature (ISB)t WDO vs. Voltage/Temperature (WD1,0 = 1, 1) VTRIP vs. Temperature (programmed at 25°C) tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0) tPURST vs. Temperature t WDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 90°C 25°C -40°C Reset (seconds) Voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 8 5 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 1.7 5.2 Reset (seconds) Voltage 2.4 3.1 3.8 4.5 90°C 25°C -40°C 200 195 190 185 180 175 170 165 160 -40 25 90 Degrees °C 205Time (ms) 90°C 25°C -40°C 200 195 190 185 180 175 170 165 160 205 Reset (seconds) Voltage X5323, X5325

19 FN8131.1 October 27, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X5323, X5325

20 FN8131.1 October 27, 2005 PACKAGING INFORMATION NOTE: 1. ALL DIMENSIONS IN INCHES (I N PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane X5323, X5325

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8131.1 October 27, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X5323, X5325