X5168P-4.5A

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Document overview

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• PDF pages: 20

Technical content

Features

• L o w VCC Detection and Reset Assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V
• Long Battery Life with Low Power Consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock ™ protection - In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation
• Available Packages - 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant) Block Diagram Data Register Command Decode & Control Logic SI SO SCK CS VCC Reset Timebase Power-on and Generation VTRIP RESET/RESET Reset Low Voltage Status Register Protect Logic 4Kbits 4Kbits 8Kbits EEPROM Array WP X5168 = RESET X5169 = RESET NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 2 of 20 June 15, 2006

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE PKG. DWG # X5168PZ-4.5A (Note) X5168P Z AL X5169PZ-4.5A (Note) X5169P Z AL 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5168PI-4.5A X5168P AM X5169PI-4.5A X5169P AM -40 to 85 8 Ld PDIP MDP 0031 X5168PIZ-4.5A (Note) X5168P Z AM X5169PIZ-4.5A (Note) X5169P Z AM -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5168S8-4.5A X5168 AL X5169S8-4.5A X5169 AL 0 to 70 8 Ld SOIC MDP0027 X5168S8Z-4.5A (Note) X5168 Z AL X5169S8Z-4.5A (Note) X5169 Z AL 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5168S8I-4.5A* X5168 AM X5169S8I-4.5A X5169 AM -40 to 85 8 Ld SOIC MDP0027 X5168S8IZ-4.5A* (Note) X5168 Z AM X5169S8IZ-4.5A (Note) X5169 Z AM -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5168V14-4.5A X5168V AL X5169V14-4.5A X5169V AL 0 to 70 14 Ld TSSOP M 14.173 X5168V14Z-4.5A (Note) X5168V Z AL X5169V14Z-4.5A (Note) X5169V Z AL 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5168V14I-4.5A X5168V AM X5169V14I-4.5A X5169V AM -40 to 85 14 Ld TS SOP M14.173 X5168V14IZ-4.5A (Note) X5168V Z AM X5169V14IZ-4.5A (Note) X5169V Z AM -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5168P X5168P X5169P X5169P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP MDP0031 X5168PZ (Note) X5168P Z X5169PZ (Note) X5169P Z 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5168PI X5168P I X5169PI X5169P I -40 to 85 8 Ld PDIP MDP0031 X5168PIZ (Note) X5168P Z I X5169PIZ (Note) X5169P Z I -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5168S8* X5168 X5169S8* X5169 0 to 70 8 Ld SOIC MDP0027 X5168S8Z* (Note) X5168 Z X5169S8Z* (Note) X5169 Z 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5168S8I* X5168 I X5169S8I* X5169 I -40 to 85 8 Ld SOIC MDP0027 X5168S8IZ* (Note) X5168 Z I X5169S8IZ* (Note) X5169 Z I -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5168V14* X5168V X5169V14* X5169V 0 to 70 14 Ld TSSOP M14.173 X5168V14Z* (Note) X5168V Z X5169V14Z* (Note) X5169V Z 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5168V14I* X5168V I X5169V14I* X5169V I -40 to 85 14 Ld TSSOP M14.173 X5168V14IZ* (Note) X5168V Z I X5169V14IZ* (Note) X5169V Z I -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5168PZ-2.7A (Note) X5168P Z AN X5169PZ-2.7A (Note) X5169P Z AN 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5168PI-2.7A X5168P AP X5169PI-2.7A X5169P AP -40 to 85 8 Ld PDIP MDP 0031 X5168PIZ-2.7A (Note) X5168P Z AP X5169PIZ-2.7A (Note) X5169P Z AP -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5168S8-2.7A* X5168 AN X5169S8-2.7A X5169 AN 0 to 70 8 Ld SOIC MDP0 027 X5168S8Z-2.7A* (Note) X5168 Z AN X5169S8Z-2.7A (Note) X5169 Z AN 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5168S8I-2.7A* X5168 AP X5169S8I-2.7A X5169 AP -40 to 85 8 Ld SOIC MD P0027 X5168S8IZ-2.7A (Note) X5168 Z AP X5169S8IZ-2.7A (Note) X5169 Z AP -40 to 85 8 Ld SOIC (Pb-free) MDP0027

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 3 of 20 June 15, 2006 Pin Configuration X5168V14Z-2.7A (Note) X5168V Z AN X5169V14Z-2.7A (Note) X5169V Z AN 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5168V14I-2.7A X5168V AP X5169V14I-2.7A X5169V AP -40 to 85 14 Ld TS SOP M14.173 X5168V14IZ-2.7A (Note) X5168V Z AP X5169V14IZ-2.7A (Note) X5169V Z AP -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5168PZ-2.7 (Note) X5168P Z F X5169PZ-2.7 (Note) X5169P Z F 8 Ld PDIP (Pb-free) MDP0031 X5168PI-2.7 X5168P G X5169PI-2.7 X5169P G -40 to 85 8 Ld PDIP MDP0031 X5168PIZ-2.7 (Note) X5168P Z G X5169PIZ-2.7 (Note) X5169P Z G 8 Ld PDIP (Pb-free) MDP0031 X5168S8-2.7* X5168 F X5169S8-2.7* X5169 F 0 to 70 8 Ld SOIC MDP0027 X5168S8Z-2.7* (Note) X5168 Z F X5169S8Z-2.7* (Note) X5169 Z F 8 Ld SOIC (Pb-free) MDP0027 X5168S8I-2.7* X5168 G X5169S8I-2.7* X5169 G -40 to 85 8 Ld SOIC MDP 0027 X5168S8IZ-2.7* (Note) X5168 Z G X5169S8IZ-2.7* (Note) X5169 Z G 8 Ld SOIC (Pb-free) MDP0027 X5168V14-2.7* X5168V F X5169V14-2.7* X5169V F 0 to 70 14 Ld TSSOP M14 .173 X5168V14Z-2.7* (Note) X5168V Z F X5169V14Z-2.7* (Note) X5169V Z F 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5168V14I-2.7* X5168V G X5169V14I-2.7* X5168V G -40 to 85 14 Ld TSSO P M14.173 X5168V14IZ-2.7* (Note) X5168V Z G X5169V14IZ-2.7* (Note) X5168V Z G -40 to 85 14 Ld TSSOP (Pb-free) M14.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T1" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE PKG. DWG #

8 LD SOIC/PDIP

14 LD TSSOP

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 4 of 20 June 15, 2006 Pin Description PIN (SOIC/PDIP) PIN TSSOP NAME FUNCTION 11 C S Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 36 W P Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the watchdog timer control and the memory write protect bits.

47 V SS Ground

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power- up at about 1V and remains active for 200ms after the power supply stabilizes. 3-5,10-12 NC No internal connections

minimum data retention of 100 years. condition and after the completion of a valid write cycle. The RDSR instruction provides access to the status register. Note: *Instructions are shown MSB in leftmost pos ition. Instructions are transferred MSB first. TABLE 1. INSTRUCTION SET TABLE 2. BLOCK PROTECT MATRIX

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

and can be reset by the WRDS instruction. block lock protection of that portion of memory. instructions. The flag bit is automatically reset upon power-up. provide an in-circuit programmable ROM function (Table 2). status register write operations. from inadvertent corruption. nonvolatile writes to the device’s status register. attempts to the status register. grounded and still be able to program the status register. changes now require a hardware change. FIGURE 5. READ EEPROM ARRAY SEQUENCE

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 9 of 20 June 15, 2006 Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be “0”. While the write is in progress following a status register or EEPROM sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. Operational Notes The device powers-up in the following state:

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes:
• A WREN instruction must be issued to set the write enable latch.
• C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle.

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 12 of 20 June 15, 2006 Absolute Maximum Ratings Reco mmended Operating Conditions Temperature Range Supply Voltage Limits CAUTION: Stresses above those listed under “Absolute Maximum Rating s” may cause permanent damage to the device. This is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP MAX ICC1 VCC write current (active) SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 5m A ICC2 VCC read current (active) SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 0.4 mA ISB VCC standby current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC = 5.5V 1µ A ILI Input leakage current V IN = VSS to VCC 0 . 1 1 0 µ A ILO Output leakage current V OUT = VSS to VCC 0.1 10 µA VIL (NOTE 1) Input LOW voltage -0.5 V CC x 0.3 V VIH (NOTE 1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage V CC > 3.3V, IOL = 2.1mA 0.4 V VOL2 Output LOW voltage 2V < V CC  3.3V, IOL = 1mA 0.4 V VOL3 Output LOW voltage V CC  2V, IOL = 0.5mA 0.4 V VOH1 Output HIGH voltage V CC > 3.3V, IOH = -1.0mA V CC - 0.8 V VOH2 Output HIGH voltage 2V < V CC  3.3V, IOH = -0.4mA V CC - 0.4 V VOH3 Output HIGH voltage V CC 2V, IOH = -0.25mA V CC - 0.2 V VOLS Reset output LOW voltage I OL = 1mA 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V. SYMBOL TEST CONDITIONS MAX. UNIT COUT (NOTE 2) Output capacitance (SO, RESET/RESET) V OUT = 0V 8 pF CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP)V IN = 0V 6 pF NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 13 of 20 June 15, 2006 Equivalent A.C. Load Circuit at 5V VCC Output 100pF 4.6k RESET/RESET 30pF 2.06k 3.03k A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 SYMBOL PARAMETER 2.7-5.5V UNITMIN MAX SERIAL INPUT TIMING fSCK Clock frequency 0 2 MHz tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 200 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) Input rise time 100 ns tFI(3) Input fall time 100 ns tCS CS deselect time 500 ns tWC(4) Write cycle time 10 ms

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 14 of 20 June 15, 2006 Serial Input Timing Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance SYMBOL PARAMETER 2.7-5.5V UNITMIN MAX fSCK Clock frequency 0 2 MHz tDIS Output disable time 250 ns tV Output valid from clock low 200 ns tHO Output hold time 0 ns tRO(3) Output rise time 100 ns tFO(3) Output fall time 100 ns SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 15 of 20 June 15, 2006 Power-Up and Power-Down Timing RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions VCC tPURST tPURST tR tF tRPD RESET (X5168)

0 Volts

RESET (X5169) SYMBOL PARAMETER MIN TYP MAX UNIT VTRIP Reset trip point voltage, X5168-4.5A, X5168-4.5A Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V V TH VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV tPURST Power-up reset time out 100 200 280 ms tRPD(5) VCC detect to reset/output 500 ns tF(5) VCC fall time 100 µs tR(5) VCC rise time 100 µs VRVALID Reset valid VCC 1V SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 16 of 20 June 15, 2006 VTRIP Reset Conditions SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO VCC* *VCC > Programmed VTRIP VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP program voltage setup time 1 µs tVPH SCK VTRIP program voltage hold time 1 µs tP VTRIP program pulse width 1µ s tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms tVPO SCK VTRIP program voltage off time before next cycle 0 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) -25 +25 mV Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested.

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 17 of 20 June 15, 2006 Typical Performance Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer Off (VCC = 3V, 5V) -40C 25C 90C Temp (°C) Isb (µA) VCC Supply Current vs. Temperature (ISB) VTRIP vs. Temperature (programmed at 25°C) tPURST vs. Temperature 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 8 5 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 200 195 190 185 180 175 170 165 160 -40 25 90 Degrees °C 205Time (ms)

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 18 of 20 June 15, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

X5168, X5169 (Replaces X25268, X25169) FN8130 Rev 2.00 Page 19 of 20 June 15, 2006 Plastic Dual-In-Line Packages (PDIP) NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the l eads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES N 8 14 16 18 20 Reference Rev. B 2/99 D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

FN8130 Rev 2.00 Page 20 of 20 June 15, 2006 X5168, X5169 (Replaces X25268, X25169) Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7  0o 8o 0o 8o - Rev. 2 4/06