X5165S8

X5163 XICOR | Alldatasheet

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REV 1.1 3/5/01 Characteristics subject to change without notice. 1 of 21 www.xicor.com Preliminary Information Replaces X25163/X25165 X5163/X5165 CPU Supervisor with 16Kbit SPI EEPROM

FEATURES

• Selectable watchdog timer
• L o w V CC detection and reset assertion —Five standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
• Determine watchdog or low voltage reset with a volatile flag bit
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read
• 16Kbits of EEPROM
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock protection —In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages —14-lead TSSOP, 8-lead SOIC

DESCRIPTION

These devices combine four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcon- troller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Five industry standard V TRIP thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Reset & Watchdog Timebase Power on and GenerationVTRIP RESET/RESET Reset Low Voltage Status Register Protect Logic 4K Bits 4K Bits 8K Bits EEPROM Array Watchdog Transition Detector WP X5163 = RESET X5165 = RESET VCC Threshold Reset Logic

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 2 of 21REV 1.1 3/5/01 www.xicor.com PIN DESCRIPTION PIN CONFIGURATION Pin (SOIC/PDIP) Pin TSSOP Name Function 1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch- dog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET /RESET going active.

22 S O

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

36 W P

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits. 47 V SS Ground

58 S I

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 6 9 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and out- put. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 7 13 RESET RESET Reset Output RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 200ms. RESET/ RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power up at 1V and remains active for 200ms after the power supply stabilizes. 81 4 V CC Supply Voltage 3-5,10- NC No internal connections 8-Lead SOIC/PDIP CS/WDI WP SO RESET/RESET VCC 14-Lead TSSOP SO WP VSS RESET/RESET SCK SI NC VCC NC X5163/65 VSS SCK CS/WDI NC NC NC NC X5163/65 SI

Characteristics subject to change without notice. Figure 3. V

Characteristics subject to change without notice. Figure 4. Sample VTRIP Reset Circuit col allowing operation on a simple four-wire bus. and a minimum data retention of 100 years. with data being clocked in on the rising edge of SCK. must be LOW during the entire operation. after the completion of a valid Write Cycle. “0”, no write is in progress.

Table 1. Instruction Set Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. Table 2. Block Protect Matrix

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

set HIGH and when WEL = 0 the latch is reset LOW. protection of that portion of memory. programmed with the WRSR instruction. a watchdog time out or power failure.

Figure 5. Read EEPROM Array Sequence bits from inadvertent corruption. WP pin is LOW and the nonvolatile bit WPEN is “1”. ables subsequent write attempts to the Status Register. changes now require a hardware change. higher address after each byte of data is shifted out. EEPROM Array Sequence (Figure 1). of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 2). then the WREN instruction is clocked into the device.

go low and remain low for the duration of the operation. have been previously written. not be completed (Figure 4). – The device is in the low power standby state. an active state and receive an instruction. – The Write Enable Latch is reset. order to start a nonvolatile write cycle. Figure 6. Read Status Register Sequence

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 10 of 21REV 1.1 3/5/01 www.xicor.com SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 11 of 21REV 1.1 3/5/01 www.xicor.com ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Device Option Supply Voltage –2.7 or -2.7A 2.7V to 5.5V Blank or -4.5A 4.5V-5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Unit Test ConditionsMin. Typ. Max. ICC1 VCC Write Current (Active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ICC2 VCC Read Current (Active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ISB1 VCC Standby Current WDT = OFF 1 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB2 VCC Standby Current WDT = ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC Standby Current WDT = ON 20 µA CS = VCC, VIN = VSS or VCC, VCC = 3.6V ILI Input Leakage Current 0.1 10 µA V IN = VSS to VCC ILO Output Leakage Current 0.1 10 µA V OUT = VSS to VCC VIL (1) Input LOW Voltage –0.5 V CC x 0.3 V VIH (1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < V CC ≤ 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V V CC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage V CC – 0.8 V V CC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage V CC – 0.4 V 2V < V CC ≤ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage V CC – 0.2 V V CC ≤ 2V, IOH = –0.25mA VOLS Reset Output LOW Voltage 0.4 V I OL = 1mA

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 12 of 21REV 1.1 3/5/01 www.xicor.com CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. Symbol Test Max. Unit Conditions COUT (2) Output Capacitance (SO, RESET, RESET) 8 pF V OUT = 0V CIN (2) Input Capacitance (SCK, SI, CS, WP) 6 pF V IN = 0V EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS Output 100pF 3.3KΩ RESET/RESET 30pF 1.64KΩ 1.64KΩ Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing Symbol Parameter 2.7-5.5V UnitMin. Max. fSCK Clock Frequency 0 2 MHz tCYC Cycle Time 500 ns tLEAD CS Lead Time 250 ns tLAG CS Lag Time 250 ns tWH Clock HIGH Time 200 ns tWL Clock LOW Time 200 ns tSU Data Setup Time 50 ns tH Data Hold Time 50 ns tRI (3) Input Rise Time 100 ns tFI (3) Input Fall Time 100 ns tCS CS Deselect Time 500 ns tWC (4) Write Cycle Time 10 ms

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 13 of 21REV 1.1 3/5/01 www.xicor.com Serial Input Timing Serial Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Symbol Parameter 2.7–5.5V UnitMin. Max. fSCK Clock Frequency 0 2 MHz tDIS Output Disable Time 250 ns tV Output Valid from Clock Low 200 ns tHO Output Hold Time 0 ns tRO (3) Output Rise Time 100 ns tFO (3) Output Fall Time 100 ns SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance SCK CS SO SI MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 14 of 21REV 1.1 3/5/01 www.xicor.com Power-Up and Power-Down Timing RESET Output Timing Notes: (5) This parameter is periodically sampled and not 100% tested. (6) Typical values not tested. CS/WDI vs. RESET/RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A Reset Trip Point Voltage, X5163, X5165 Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A Reset Trip Point Voltage, X5163-2.7, X5165-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.92 2.63 4.75 4.5 3.0 2.7 V V TH VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV tPURST Power-up Reset Time Out 100 200 280 ms tRPD (5) VCC Detect to Reset/Output 500 ns tF (5) VCC Fall Time 100 µs tR (5) VCC Rise Time 100 µs VRVALID Reset Valid VCC 1V VCC tPURST tPURST tR tF tRPD RESET (X5163)

0 Volts

RESET (X5165) CS/WDI tCST RESET tWDO tRST RESET tWDO tRST

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 15 of 21REV 1.1 3/5/01 www.xicor.com RESET/RESET Output Timing VTRIP Set Conditions VTRIP Reset Conditions Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time Out 100 200 300 ms SCK SI VP VP CS tVPS tVPH tPtVPS tVPH tRP tVPO tVPO tTSU tTHD VTRIPVCC SCK SI VCC VP CS tVPS tVPH tPtVPS tVP1 tRP tVPO tVPO tTSU tTHD VTRIP VCC

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 16 of 21REV 1.1 3/5/01 www.xicor.com VTRIP Programming Specifications: VCC = 1.7–5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK VTRIP Program Voltage Setup time 1 µs tVPH SCK VTRIP Program Voltage Hold time 1 µs tP VTRIP Program Pulse Width 1 µs tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tRP VTRIP Program Cycle Recovery Period (Between successive programming cycles) 10 ms tVPO SCK VTRIP Program Voltage Off time before next cycle 0 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied—V TRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied—V ta1)—V TRIP) (Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested.

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 17 of 21REV 1.1 3/5/01 www.xicor.com Watchdog Timer On (V CC = 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer Off (VCC = 3V, 5V) –40 25 90 Temp (°C) Isb (µA) VCC Supply Current vs. Temperature (ISB)t WDO vs. Voltage/Temperature (WD1, 0 = 1, 1) VTRIP vs. Temperature (programmed at 25°C) t WDO vs. Voltage/Temperature (WD1, 0 = 1, 0) tPURST vs. Temperature t WDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 90°C 25°C –40°C Reset (seconds) Voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 8 5 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 1.7 5.2 Reset (seconds) Voltage 2.4 3.1 3.8 4.5 90°C 25°C –40°C 200 195 190 185 180 175 170 165 160 –40 25 90 Degrees °C 205Time (ms) 90°C 25°C –40°C 200 195 190 185 180 175 170 165 160 205 Reset (seconds) Voltage

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 18 of 21REV 1.1 3/5/01 www.xicor.com PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 19 of 21REV 1.1 3/5/01 www.xicor.com PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 20 of 21REV 1.1 3/5/01 www.xicor.com

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) 8L SOIC 0 oC - 70oC X5163S8-4.5A X5165S8-4.5A -40oC - 85oC X5163S8I-4.5A 14L TSSOP 0 oC - 70oC -40oC - 85oC 8L SOIC 0 oC - 70oC X5163S8 X5165S8 -40oC - 85oC X5163S8I 14L TSSOP 0 oC - 70oC X5163V14 -40oC - 85oC -40oC - 85oC 14L TSSOP 0 oC - 70oC -40oC - 85oC -40oC - 85oC 14L TSSOP 0 oC - 70oC X5163V14-2.7 -40oC - 85oC Blank = 8-Lead SOIC V = 14 Lead TSSOP Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 A = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 IA = 5V ±10%, –40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 FA = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.55-2.7 GA = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.85-3.0 WX5163/65 X

X5163/X5165 – Preliminary Information Characteristics subject to change without notice. 21 of 21REV 1.1 3/5/01 www.xicor.com ©Xicor, Inc. 2001 Patents PendingLIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.