X5163V14I-2.7

X5163_06 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• Selectable watchdog timer
• L o w VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low V CC reset threshold voltage using special programming sequence - Reset signal valid to V CC = 1V
• Determine watchdog or low voltage reset with a volatile flag bit
• Long battery life with low power consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
• 16kbits of EEPROM
• Built-in inadvertent write protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or al l of EEPROM array with Block Lock™ protection - In-circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages: 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant) Pinouts

8 Ld SOIC/PDIP

14 Ld TSSOP

V CC NC X5163, X5165 VSS SCK CS/WDI NC NC NC NC SI X5163, X5165 X5163, X5165 Data Sheet June 1, 2006

2 FN8128.3 June 1, 2006

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE PKG. DWG. # X5163P X5163P X5165P X5165P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP MDP0031 X5163PZ (Note) X5163P Z X5165PZ (Note) X5165P Z 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5163PI X5163P I X5165PI X5165P I -40 to 85 8 Ld PDIP MDP0031 X5163PIZ (Note) X5163P Z I X5165PIZ (Note) X5165P Z I -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5163S8* X5163 X5165S8* X5165 0 to 70 8 Ld SOIC MDP0027 X5163S8Z* (Note) X5163 Z X5165S8Z* (Note) X5165 Z 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5163S8I* X5163 I X5165S8I* X5165 I -40 to 85 8 Ld SOIC MDP0027 X5163S8IZ* (Note) X5163 Z I X5165S8IZ* (Note) X5165 Z I -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5163V14* X5163V X5165V14* X5165V 0 to 70 14 Ld TSSOP M14.173 X5163V14Z* (Note) X5163V Z X5165V14Z* (Note) X5165V Z 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5163V14I* X5163V I X5165V14I* X5165V I -40 to 85 14 Ld TSSOP M14.173 X5163V14IZ* (Note) X5163V Z I X5165V14IZ* (Note) X5165V Z I -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5163PZ-2.7 (Note) X5163P Z F X5165PZ-2.7 (Note) X5165P Z F 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5163PI-2.7 X5163P G X5165PI-2.7 X5165P G -40 to 85 8 Ld PDIP MDP0031 X5163PIZ-2.7 (Note) X5163P Z G X5165PIZ-2.7 (Note) X5165P Z G -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5163S8-2.7* X5163 F X5165S8-2.7* X5165 F 0 to 70 8 Ld SOIC MDP0027 X5163S8Z-2.7* (Note) X5163 Z F X5165S8Z-2.7* (Note) X5165 Z F 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5163S8I-2.7* X5163 G X5165S8I-2.7* X5165 G -40 to 85 8 Ld SOIC MDP0027 X5163S8IZ-2.7* (Note) X5163 Z G X5165S8IZ-2.7* (Note) X5165 Z G -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5163V14-2.7* X5163V F X5165V14-2.7* X5165V F 0 to 70 14 Ld TSSOP M14.173 X5163V14Z-2.7* (Note) X5163V Z F X5165V14Z-2.7* (Note) X5165V Z F 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5163V14I-2.7* X5163V G X5165V14I-2.7* X5165V G -40 to 85 14 Ld TSSOP M14.173 X5163V14IZ-2.7* (Note) X5163V Z G X5165V14IZ-2.7* (Note) X5165V Z G -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5163PZ-2.7A (Note) X5163P Z AN X5165PZ-2.7A (Note) X5165P Z AN 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5163PI-2.7A X5163P AP X5165PI-2.7A X5165P AP -40 to 85 8 Ld PDIP MDP0031 X5163PIZ-2.7A (Note) X5163P Z AP X5165PIZ-2.7A (Note) X5165P Z AP -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5163S8-2.7A* X5163 AN X5165S8-2.7A X5165 AN 0 to 70 8 Ld SOIC MDP0027 X5163, X5165

3 FN8128.3 June 1, 2006 X5163S8Z-2.7A* (Note) X5163 Z AN X5165S8Z-2.7A (Note) X5165 Z AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5163S8I-2.7A X5163 AP X5165S8I-2.7A X5165 AP -40 to 85 8 Ld SOIC MDP0027 X5163S8IZ-2.7A (Note) X5163 Z AP X5165S8IZ-2.7A (Note) X5165 Z AP -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5163V14-2.7A X5163V AN X5165V14-2.7A X5165V AN 0 to 70 14 Ld TSSOP M14.173 X5163V14Z-2.7A (Note) X5163V Z AN X5165V14Z-2.7A (Note) X5165V Z AN 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5163V14I-2.7A X5163V AP X5165V14I-2.7A X5165V AP -40 to 85 14 Ld TSSOP M14.173 X5163V14IZ-2.7A (Note) X5163V Z AP X5165V14IZ-2.7A (Note) X5165V Z AP -40 to 85 14 Ld TSSOP (Pb-free) M14.173 X5163PZ-4.5A (Note) X5163P Z AL X5165PZ-4.5A (Note) X5165P Z AL 0 to 70 8 Ld PDIP (Pb-free) MDP0031 X5163PI-4.5A X5163P AM X5165PI-4.5A X5165P AM -40 to 85 8 Ld PDIP MDP0031 X5163PIZ-4.5A (Note) X5163P Z AM X5165PIZ-4.5A (Note) X5165P Z AM -40 to 85 8 Ld PDIP (Pb-free) MDP0031 X5163S8-4.5A X5163 AL X5165S8-4.5A X5165 AL 0 to 70 8 Ld SOIC MDP0027 X5163S8Z-4.5A (Note) X5163 Z AL X5165S8Z-4.5A (Note) X5165 Z AL 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5163S8I-4.5A X5163 AM X5165S8I-4.5A X5165 AM -40 to 85 8 Ld SOIC MDP0027 X5163S8IZ-4.5A (Note) X5163 Z AM X5165S8IZ-4.5A (Note) X5165 Z AM -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5163V14-4.5A X5163V AL X5165V14-4.5A X5165V AL 0 to 70 14 Ld TSSOP M14.173 X5163V14Z-4.5A (Note) X5163V Z AL X5165V14Z-4.5A (Note) X5165V Z AL 0 to 70 14 Ld TSSOP (Pb-free) M14.173 X5163V14I-4.5A X5163V AM X5165V14I-4.5A X5165V AM -40 to 85 14 Ld TSSOP M14.173 X5163V14IZ-4.5A (Note) X5163V Z AM X5165V14IZ-4.5A (Note) X5165V Z AM -40 to 85 14 Ld TSSOP (Pb-free) M14.173 *Add "T1" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) V TRIP RANGE TEMP RANGE (°C) PACKAGE PKG. DWG. # X5163, X5165

4 FN8128.3 June 1, 2006 Block Diagram Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP RESET/RESET Reset Low Voltage Status Register Protect Logic 4K Bits 4K Bits 8K Bits EEPROM Array Watchdog Transition Detector WP X5163 = RESET X5165 = RESET VCC Threshold Reset Logic Pin Description PIN (SOIC/PDIP) PIN TSSOP NAME FUNCTION 1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 36 W P Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits.

47 V SS Ground

58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 7 13 RESET / RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power- up at 1V and remains active for 200ms after the power supply stabilizes. 81 4 V CC Supply Voltage 3-5,10-12 NC No internal connections X5163, X5165

operation on a simple four-wire bus. minimum data retention of 100 years. LOW during the entire operation. TABLE 1. INSTRUCTION SET NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 2. BLOCK PROTECT MATRIX

0 X X Protected Protected Protected

1 X 1 Protected Writable Writable

instruction and can be reset by the WRDS instruction. disable block lock protection of that portion of memory. programmed with the WRSR instruction. all Status Register Write Operations. from inadvertent corruption. disables nonvolatile writes to the device’s Status Register. subsequent write attempts to the Status Register. FIGURE 5. READ EEPROM ARRAY SEQUENCE

9 FN8128.3 June 1, 2006 When WP is HIGH, all functions, including nonvolatile writes to the Status Register operate normally. Setting the WPEN bit in the Status Register to “0” blocks the WP pin function, allowing writes to the Status Register when WP is HIGH or LOW. Setting the WPEN bit to “1” while the WP pin is LOW activates the Progr ammable ROM mode, thus requiring a change in the WP pin prior to subsequent Status Register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the Status Regi ster. Manufacturing can then load Configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the “OTP mode” by setting the WPEN bit. Data changes now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 5). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 6). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 0 and 1 must be “0”. While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. Operational Notes The device powers-up in the following state:

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for t PURST. Data Protection The following circuitry has been included to prevent inadvertent writes:
• A WREN instruction must be issued to set the Write Enable Latch.
• C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle. X5163, X5165

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

12 FN8128.3 June 1, 2006 Absolute Maximum Ratings Recommended Operating Conditions Voltage on any pin with CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Specifications Over operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP MAX ICC1 VCC Write Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 5m A ICC2 VCC Read Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 0.4 mA ISB1 VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC =5 . 5 V 1 µ A ISB2 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC =5 . 5 V 5 0 µ A ISB3 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC =3 . 6 V 2 0 µ A ILI Input Leakage Current V IN = VSS to VCC 0.1 10 µA ILO Output Leakage Current V OUT = VSS to VCC 0.1 10 µA VIL(1) Input LOW Voltage -0.5 V CC x 0.3 V VIH(1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage V CC > 3.3V, IOL = 2.1mA 0.4 V VOL2 Output LOW Voltage 2V < V CC ≤ 3.3V, IOL = 1mA 0.4 V VOL3 Output LOW Voltage V CC ≤ 2V, IOL = 0.5mA 0.4 V VOH1 Output HIGH Voltage V CC > 3.3V, IOH = –1.0mA V CC - 0.8 V VOH2 Output HIGH Voltage 2V < V CC ≤ 3.3V, IOH = –0.4mA V CC - 0.4 V VOH3 Output HIGH Voltage V CC ≤ 2V, IOH = –0.25mA V CC - 0.2 V VOLS Reset Output LOW Voltage I OL = 1mA 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST MAX. UNIT CONDITIONS COUT(2) Output Capacitance (SO, RESET, RESET) 8 pF V OUT = 0V CIN(2) Input Capacitance (SCK, SI, CS, WP)6 p F V IN = 0V NOTES: 1. V IL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. X5163, X5165

1. This parameter is periodically sampled and not 100% tested.

WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. TABLE 3. SERIAL OUTPUT TIMING

0 Volts

TABLE 4. POWER-UP AND POWER-DOWN TIMING

1. This parameter is periodically sampled and not 100% tested.
2. Typical values not tested.

FIGURE 12. CS/WDI VS. RESET/RESET TIMING

17 FN8128.3 June 1, 2006 VTRIP Programming Specifications: VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP Program Voltage Setup time 1 µs tVPH SCK VTRIP Program Voltage Hold time 1 µs tP VTRIP Program Pulse Width 1µ s tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tRP VTRIP Program Cycle Recovery Period (Between successive programming cycles) 10 ms tVPO SCK VTRIP Program Voltage Off time before next cycle 0 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. X5163, X5165

19 FN8128.3 June 1, 2006 X5163, X5165 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

20 FN8128.3 June 1, 2006 X5163, X5165 Plastic Dual-In-Line Packages (PDIP) NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the l eads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES N 8 14 16 18 20 Reference Rev. B 2/99 D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8128.3 June 1, 2006 X5163, X5165 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06