X5114

X5114 XICOR | Alldatasheet

Document overview

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Technical content

Ó Xicor, Inc. 1994 - 1997 Patents Pending 7054-1.2 10/29/00 T13/C8/D24 SH Characteristics subject to change without notice X5114 System Controller

FEATURES

• Simplifies Backplane Communications
• Monitor Fault and “Hot Docking” Conditions
• Ten Level Selectable Input Threshold
• Two Fully Redundant SPI Serial I/O Ports
• Programmable Output or Input Port Pins —16 General I/O pins —8 bit Port with 4 Handshake Modes
• Single Read Input Mode
• Multiple Read Input Mode
• Output Mode
• Bidirectional Mode —Port Tristate Control
• Programmable Interrupt and Mask Options
• 8-bit Direct Address Decoder allows Cascaded 255+ devices on one SPI bus
• 4K bits of EEPROM with 32 byte page write
• Default Output Data on Port at Power-up
• High Reliability EEPROM —Endurance - 10 Data Changes —Data Retention - 100 years
• 44-Pin PLCC, 48-Lead TQFP

DESCRIPTION

The X5114 is a single-chip system controller that is used in applications such as multiprocessing, telecommunica- tions, data communications, cable systems, set top boxes, etc. The chip can implement features such as backplane communication, hot docking, cable diagnos- tics, etc. The X5114 makes extensive use of nonvolatile memory with 4,096 bits of general purpose EEPROM, nonvolatile configuration registers, and nonvolatile programming of the port pins. The ports can be set up as sixteen general I/Os with pin selectable data direction (including eight inputs with nonvolatile threshold selections) or as an eight bit port with handshake. The chip is controlled via two redundant 2MHz SPI serial ports. A sophisticated interrupt controller provides notification of a failed SPI command, changing conditions on an input, handshake status, and I/O errors. Interrupts are maskable. On-chip EEPROM provides nonvolatile storage of system status, manufacturing information, board ID or other parameters. FUNCTIONAL DIAGRAM CSa SCKa SIa SOa CSb SCKb SIb SOb CSO CSC Port Regs

256 X 8

SPI_A SPI_B Address Select Decode (PB7-PB4) Output Tristate = EEPROM Handshake Port A

PIN CONFIGURATION PIN NAMES PIN DESCRIPTIONS CSa /CSb (SPI A/B Chip Select) These are schmitt trigger input pins used by the host system to select the X5114 SPI port. A HIGH to LOW (falling) transition on CSa or CSb starts the X5114 serial access. Both of these pins at logic “1” deselects the device and places the SOa and SOb pins in a high impedance state. In the event of a stuck LOW on either of these pins, a HIGH to LOW transition on the other chip select will override the inoperative serial port. SCKa/SCKb (SPI A/B Serial Clock) These are schmitt trigger input pins used by the host system to supply the SPI serial clock. Only clock mode 3 is supported by X5114. When inactive, the SPI serial clock is to be driven to a logic HIGH level. SIa/SIb (SPI A/B Serial Input) These are schmitt trigger, serial data inputs. They receive device address, opcode, and data from the host system at the rising edge of the serial clock (i.e. SCKa or SCKb). SOa/SOb (SPI A/B Serial Output) These are push-pull serial data outputs. They shift out data after each falling edge of the serial clock and are stable on the rising edge of the serial clock (i.e. SCKa or SCKb). When the device is not outputting data or is in standby, the serial data outputs will be in a high impedance state. PA3 PA2 PA1 VCC PA5 PA6 NC PA0 PA4 PCE PA7 VSS IRQB SOb SCKb SOa SIa CSC SIb IRQA CSa SCKa CSO NC VCC PB5 PB6 PB7 NC PB3 PB2 V SS CSb PB4 PB0 PB1

44 Lead PLCC

48 Lead TQFP

V SS CSb PB4 PB0 PB1 NC PA3 PA2 PA1 VCC PA5 PA6 NC PA0 PA4 PCE PA7 CSO NC VCC NC Symbol Function SCKa, SCKb SPI A, B Serial Clock SIa, SIb, SOa, SObSPI A, B, Serial Data I/O CSa , CSb SPI A, B select A7-A0 Device Address IRQA , IRQB Interrupt A, B Outputs PCE Port Chip Enable PA7-PA0 Port A pins PB7-PB0 Port B pins CSO Chip Select Output CSC Chip Select Cascade Output V CC , V SS System Supply, Ground NC No Connection

IRQA /IRQB (Interrupt Outputs) These are open-drain Interrupt Request output pins. They are designed for multidrop wired ORing. Internal registers control the operation of the IRQ lines. See "CONTR OL/STATUS REGISTERS " on page 12 for information about the internal control registers. See “INTERR UPT REQ UESTS ” on page 23. f or an operational description of the IRQ lines. PA7-PA0/PB7-PB0 (Port A/Port B) Each bit of these 8-bit ports can be programmed to act as either an input or output. An 8-bit nonvolatile Data Direction Control Register for each port (DDRA/DDRB) controls the direction of each pin. All I/Os can enter a high impedance state when PCE is inactive. This is a configurable option (see "Port I/O Configuration Register (PCR)" on page 14 for details). In addition to the I/O programmability, Port A and Port B can be configured with handshake to provide a high speed parallel data transfer pathway. See "Handshake I/O subsystem" on page 17 for details. A7-A0 (Device Address Inputs) These inputs set a slave address for the X5114 (see "Device Addressing" on page 3 for details about addressing modes). These pins can be either hardwired or actively driven. If hardwired, these pins need to be tied to Vcc or Vss. If actively driven, the pins must be driven to V IH or V IL and they must be constant and stable during each transmission period. V CC (System Supply) This is the system supply voltage input for the device. Two V CC pins are provided. V SS (System Ground) This is the system ground voltage reference input for the device. Two V SS pins are provided. CSO (Chip Select Output) This is an output pin to indicate that the host system is in comm unication with the device. The CSO is asserted active LOW (logic “0”) whenever the device is selected by the host system. The CSO shall remain active during all comm unications and shall be de-asserted with the rising edge of either the CSa or the CSb signal. This signal helps manage access to the SPI por ts by two independent host processors. CSC (Chip Select Cascade Output) This is an output pin that enables device cascading. When receiving a NOP instruction, the device asserts the CSC signal active LOW (logic “0”). This enables another bank of devices while the device executing the NOP ignores subsequent commands and data. The rising edge of either the CSa or the CSb signal de-assertes the CSC signal. PCE (Port Chip Enable) This is a dedicated active HIGH schmitt trigger input pin to the X5114. The primary function of this input is to inhibit the generation of interrupts via an external control signal. When de-asserted (logic “0”), this input disables the IRQA and IRQB outputs. This input may be configured to both disable the IRQA and IRQB outputs and tri-state all of the Port A and Port B output drivers when de-asserted. DEVICE ARCHITECTURE The X5114 consists of two major sections. The first is a dual independent SPI serial interface. This full duplex interface provides seperate SPI ports for primary and secondary host controllers, but does not support simultaneous access. The SPI interface is compatible with industry standard SPI hardware. The host uses a command protocol to read the status of the X5114, to read and write various function registers that control device operation and to access the memory array. The second section of the X5114 consists of a sophisticated port structure. The dual 8 bit ports can be configured in a number of ways to meet the specific needs of the application. The port can serve as a general I/O, with default outputs or default input compare values. The port can also be configured with one of four different handshake options. In addition to these two main sections, an interrupt controller can be configured to report a number of conditions back to the host microcontroller. See Figure 21 on page 23. These include failed SPI communications, input changes, handshake conditions, or port interrupts. SERIAL COMMUNICATIONS Two independent Serial Peripheral Interface (SPI) Ports provide the primary comm unication connection to the X5114. Device Addressing The X5114 suppor ts a bidirectional bus oriented protocol. This protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is a slave.

X5114 is considered a slave for all operations. command) to reside on one SPI communication bus. condition. This consists of the falling edge of CSa or CSb . the CSa /CSb signal (Hardware Device Addressing). returns to the standby state. FIGURE 1. SPI Comm unications - Addressing Modes (Read example)

Hardware Device Addressing Mode In this addressing mode, all the external address pins are tied to logic “0”. The device is selected solely by the CSa or CSb pins. As soon as the CS a or CSb pin goes LOW and stays LOW , the device will be in the active state. No slave address byte is needed in this mode. Chip Select Output/Device Cascade (CSO /CSC ) The CSO and CSC output pins have two major functions. The CSO pin can be used as a chip select indicator. This signal indicates that the host processor has selected this device. The CSC signal allows the cascade of multiple banks of X5114 devices. In a cascade mode, the CSC output of a selected X5114 selects another external device by using the NOP instruction. (see "NOP " on page 7 ) Instruction Opcode The second byte transmitted to the device (or the first byte in hardware addressing mode) contains the Instruction opcode that defines the operation to be performed. All the opcode bits have been specially arranged to achieve a 2-bit difference between opcodes to reduce the possibility of inadvertent operations. Instruction Opcode OP7, OP6 “00” = memory operation, “01” = port A operation, “10” = port B operation, “11” = Control Register operation. OP5, OP4 “01” = port-related read command, “10” = port-related write command. OP3, OP2, OP1, OP0 “0000” = Configuration Register operation, “0001” = Port Latch operation, “0010” = Port Desired Value Register operation, “0100” = Port Data Direction Register operation, “1000” = Port IRQ Mask Register operation, “0011” = Port IRQ Configuration Register operation, “0101” = Port I/O Configuration Register operation, “1100” = Port IRQ Error Register operation, “1110” = Port IRQ Failed Command Register operation, “1111” = Port Registers operation. INSTRUCTION SUMMARY Each instruction must be proceeded with a HIGH to LOW transition on CSa or CSb and be terminated by a LOW to HIGH transition on CSa or CSb . There is no restriction as to which of the two SPI interface ports receives an instruction or combination of instructions. If the instruction initiates a nonvolatile write operation, as indicated in Table 1, “Instruction Opcodes,” on page 6 and in the instruction definitions, the write cycle begins at the rising edge of the CSa or CSb signals. However if the CSa or CSb goes HIGH before the device address, command, and data are sent completely (e.g. when the clock is not a multiple of eight), then no nonvolatile write cycle starts, the WEL will not reset, and there will be an incomplete transmission (i.e. a failed command). In a failed command, an interrupt signal informs the host processor of a fault condition. After completion of a nonvolatile write cycle, the circuitry automatically clears the Wr ite Enable Latch (WEL). The nonvolatile write typically takes much less than the maximum time to complete. Ho wever, the Status Register WIP bit indicates the nonvolatile wrte status. After receiving a valid address, the X5114 returns the status register contents so an host has an early end of write cycle indication. If WIP is HIGH, the write is still in progress. If WIP is LOW , the X5114 is available for continued operations. OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 MSB LSB

Table 1. Instruction Opcodes (1) In this condition, the HV Wr ite Cycle will not proceed when the X5114 is configured in the handshake mode. minimum number is 4. The minimum number of bytes required for NOP is 2. (3) All other possible instruction opcodes are illegal commands.

unlimited number of X5114s can reside in a system. Opcodes access the lower half ($000h-$0FFh). lower half of the memory array from $000h to $0FFh. can be written with data and then over-written indefinitely. Figure 2. NOP (No Operation)

“Multiple Register Read Order (RMPR),” on page 9. the CSa or CSb goes HIGH, the command terminates. Table 2. Multiple Register Read Order (RMPR) reads data from the PORT A Latch. DVRB contain the status of the output pins. “Multiple Register Wr ite Order (WMPR),” on page 11. write cycle begins after the CSa or CSb goes HIGH.

1 PAL Port A Latch

2 PBL Port B Latch

5 IAM IRQ Mask Register A

6 IBM IRQ Mask Register B

7 DVRA Desired Value Register A

8 DVRB Desired Value Register B

9 IAE IRQA Error Register

10 IBE IRQB Error Register

11 PCR Port I/O Configuration Register

12 CR Configuration Register

13 ICR IRQ Configuration Register

14 FCR IRQ Failed Command Register

Table 3. Multiple Register Write Order (WMPR) Desired Value Registers. See Figure 9 on page 10. write cycle) and triggers an output handshake sequence. the Data Direction Registers. See Figure 9 on page 10. This selects the direction of each of the port pins. provides status on port error conditions.

• an unknown or illegal instruction opcode
• an incomplete transmission of a command which can be instruction opcode, address, or data. As an exam- ple, CSa or CSb goes HIGH when the clock count is not a multiple of 8. Detection of a bad command sets a Failed Command (FC) flag in the Status Register (SR) and asserts the IRQA or IRQB signal, if enabled. The Failed Command Register contains the Error information. The host read of the Failed Command Register clears IRQA and IRQB signals and the FC flag. However, the RFCR instruction will not clear the Failed Command Register. The FCR will only store the most recent bad command if there were more than one bad command in a sequence. Also the information in the FCR is only updated when a bad command is discovered. Read Configuration RIAM, RIBM Read IRQA, IRQB Mask Register The RIAM and RIBM instructions return the contents of the respective IRQ Mask Register. See Figure 8 on page 10. RICR Read IRQ Configuration Register The RICR instruction returns the contents of the IRQ Configuration Register. See Figure 8 on page 10. RPCR Read Port I/O Configuration Register The RPCR instruction returns the contents of the PORT I/O Configuration Register. See Figure 8 on page 10. Write Order Register Description 1 DVRA Desired Value Reg. A 2 DVRB Desired Value Reg. B 3 DDRA Data Direction Reg. A 4 DDRB Data Direction Reg. B

7 PCR Port I/O Configuration Register

8 CR Configuration Register

9 ICR IRQ Configuration Register

Read Threshold/Block Lock Register The R TBL instruction returns the contents of the Threshold/Block Lock Register. See Figure 8 on page 10. Write Configuration WIAM, WIBM NONVOLATILE Write IRQA, IRQB Mask Register The WIAM and WIBM instructions write new data to the respective IRQ Mask Register. See Figure 9 on page 10. WICR NONVOLATILE Write IRQ Configuration Register The WICR instruction writes new data into the IRQ Configuration Register to change interrupt operations. See Figure 9 on page 10. WPCR NONVOLATILE Write Port I/O Configuration Register The WPCR instruction writes new data into the Port I/O Configuration Register to change the P ort I/O functionality. See Figure 9 on page 10. WTBL NONVOLATILE Write Threshold/Block Lock Register The WTBL instruction writes new data to the Threshold/Block Lock Register to select different modes of operations. See Figure 9 on page 10. CONTROL/STATUS REGISTERS The X5114 has a number of registers to monitor and control the operation of the device. Access to the control registers are via SPI Commands. The status register contains the status of the most critical operating conditions. The contents are placed on the output pins in synchronization with the incoming op code (providing the device is addressed correctly). The status register cannot be written to directly. Status Register (SR) WIP WEL PCE FC RDR XRE IRQA IRQB Volatile MSB LSB WIP Write In Progress flag. 0 no nonvolatile write cycle in progress 1 nonvolatile write cycle is in progress WEL Write Enable Latch flag 0 write enable latch has not been set 1 write enable latch is set PCE PCE Pin Input Status

0 PCE pin is at Logic 0

1 PCE pin is at Logic 1

FC Failed Command flag—Power on default = 1 0 no command failures 1 command failure (abnormal termination) RDR Receive Data Ready flag (Single Read Input and Bidirectional Modes) 0 no data is latched 1 latched data is ready for read at Port A XRE Transmit Register Empty flag (Output and Bidirectional Modes) Port A data has not been read by the external system and is not ready to accept new data from the SPI interface

1 Port A is ready to accept the new data from the

SPI interface. IRQA Interrupt Port A

0 Interrupt A is not asserted

1 Interrupt A is asserted

0 Interrupt B is not asserted

1 Interrupt B is asserted

Threshold/Block Lock Register (TBL). output data or the desired value for I/O monitoring. DVRB7 to DVRB4 are volatile in the handshake mode . Figure 10. Input Threshold Control Settings

Port Latches are read-only input registers. In the general I/O mode, decoding the SPI opcode latches data into the POR T A Latch. In the handshake mode, sensing the STRA input latches input data into the PORT A Latch. Decoding the SPI opcode always latches data into the POR T B Latch, regardless of the I/O mode. During Handshake modes, all of DDRA and the upper half of DDRB (DDRB7-DDRB4) are ignored. Port I/O Configuration Register (PCR) TRI CEM HS2 HS1 HS0 PLS EGA INVB Nonvolatile MSB LSB TRI Port tri-state configuration (Output Mode only) 0 disables tri-state operation 1 enables tri-state operation CEM Port Chip Enable Mode Configuration

0 PCE pin LOW disables IRQA and IRQB ,

1 PCE pin LOW disables IRQA and IRQB and

tri-states all port outputs (regardless of the con- tent of the DDR) HS2, HS1, HS0 General/Handshake Mode configuration 0xx general I/O mode

100 Multiple Read Input Mode

(multiple read of the Port A Latch)

101 Single Read Input mode

(single read of the Port A Latch)

110 Output Mode

111 Bidirectional Mode

PLS Handshake Pulse/Interlocked Mode config. 0 interlocked handshake mode 1 pulse handshake mode EGA Handshake strobe (STRA) active edge 0 falling edge active 1 rising edge active INVB Handshake ready (STRB, TDRE, RDRF) active level

0 Logic ‘0’ is the active level

1 Logic ‘1’ is the active level

Port Latch (PAL and PBL) PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 Volatile MSB LSB PBL7 PBL6 PBL5 PBL4 PBL3 PBL2 PBL1 PBL0 Volatile MSB LSB Port Data Direction Register (DDRA and DDRB) DDR DDR DDR DDR DDR DDR DDR DDR Nonvolatile MSB LSB DDR DDR DDR DDR DDR DDR DDR DDR Nonvolatile MSB LSB DDRA7- DDRA0 Port A Data Direction Register

0 Port I/O in an input

1 Port I/O is an output

Port B Data Direction Register

IRQ Mask Register (IAM and IBM) IRQ Error Register (IAE and IBE) IRQ Configuration Register (ICR) IAM7 IAM6 IAM5 IAM4 IAM3 IAM2 IAM1 IAM0 Nonvolatile MSB LSB IBM7 IBM6 IBM5 IBM4 IBM3 IBM2 IBM1 IBM0 Nonvolatile MSB LSB IAM7- IAM0 Port A Interrupt Mask

0 Enables the Input/Output Error - Fault Mon-

itoring on the corresponding Port A I/O pin Disables the Input/Output Error - Fault Monitoring on the corresponding Port A I/O pin. IBM7- IBM0 Port B Interrupt Mask itoring on the corresponding Port B I/O pin Disables the Input/Output Error - Fault Monitoring on the corresponding Port B I/O pin. IAE7 IAE6 IAE5 IAE4 IAE3 IAE2 IAE1 IAE0 Volatile (Read only) MSB LSB IBE7 IBE6 IBE5 IBE4 IBE3 IBE2 IBE1 IBE0 Volatile (Read only) MSB LSB IAE7– IAE0 Interrupt A Error Flags 0 no, the Port A I/O has no error (Fault Monitoring) 1 yes, the Port A I/O has an error (Fault Monitoring) IBE7– IBE0 Interrupt B Error Flags 0 no, the Port B I/O has no error (Fault Monitoring) 1 yes, the Port B I/O has an error (Fault Monitoring)

0 ORAB ENFC ERDR EXRE EIOE ENA ENB

IRQA and IRQB individually represent Port A and Port B interrupt status and are not ORed together

1 IRQA

and IRQB provide redundancy and are ORed together ENFC Failed Command Interrupt configuration 0 disables interrupt generated by Failed Com- mand 1 enables interrupt generated by Failed Com- mand ERDR Receive Data Ready interrupt configuration 0 disables IRQA generated by the RDR flag 1 enables IRQA generated by the RDR flag. EXRE XRE interrupt configuration 0 disables IRQA generated by XRE flag 1 enables IRQA generated by XRE flag EIOE Input/Output Error interrupt configuration 0 disables interrupt generated by Input/Output Error 1 enables interrupt generated by Input/Output Error ENA IRQA output configuration 0 disables IRQA interrupt output 1 enables IRQA interrupt output ENB IRQB output configuration 0 disables IRQB interrupt output 1 enables IRQB interrupt output

incomplete transmission of the address or data. of four Handshake Configurations. are always used as general I/O. Register and by the PCE (Port Chip Enable) pin. into both the volatile and nonvolatile parts of the register. Figure 11. General I/O and Fault Monitoring Configuration (Port A)

• Single Read Input
• Multiple Read Input
• Output
• Bi-directional The handshake I/O subsystem efficiently supports high speed data transfers between an external system and a controlling master through the SPI ports of the X5114. These four handshake modes support a variety of 8-bit parallel data applications, such as interfacing to a simple 8-bit latch, an A/D converter or a microcontroller. The 8-bit parallel data path uses Port A, with the handshake I/O signals interfacing to Port B. For applications which do not require high speed 8-bit parallel data transfer, the handshake functions can generally be ignored. When handshake functions are used, the remaining Port B pins serve as general I/O without interfering with the handshake functions. Table 4 on page 17 shows the different functions of port B pins for different port I/O handshake modes.

Table 4. Special Port B Pins in Handshake Modes

• Port A is the high speed input data port.
• STRA (PB7) is the stobe input. An external device uses this signal to write new data into the Port A Latch. The EGA bit selects which edge of the STRA input will register the input data.
• TDRE (PB6) is the ready output signal. This signal noti- fies the external device that new data can be written. Reading the port data via the SPI port automatically resets the TDRE signal. The invert bit (INVB) sets the active level of the TDRE output signal.
• RDR Flag - The STRA signal sets the RDR flag in the Status register. Once set, the RDR flag automatically inhibits further writes into PORT A from the external

An A/D converter connects to the X5114 parallel port. output signal that initiates a new A/D conversion cycle.

• Port A is the high speed input data port.
• STRB (PB6) is the strobe output. The invert bit (INVB) sets the active level of STRB in the multiple read mode. Reading Port A data through the SPI port automatically

Figure 14. Multiple Read Input Mode - SPI Read

D.C. OPERATING CHARACTERISTICS TA = -40°C to +85°C, Vcc = +4.5V to +5.5V, unless otherwise specified. (1) VIL min. and VIH max. are for reference only and not tested. Symbol Parameter Min Max Unit ICC Vcc Supply Current, fSCKa or fSCKb = 2.0MHz; Vcc = +5.5V; SOa, SOb = Open (Active, Non-Volatile Write States only) 5 mA ISB Standby Current, Vcc = +5.5V; VIN = Vss or Vcc; CSa = CSb = Vcc; 2 mA ILI Input Leakage current, VIN = Vss to Vcc 10 uA ILO Output Leakage current, VOUT = Vss to Vcc 10 uA VIL (1) Input Low Voltage -0.5 Vcc x 0.3 V VIH (1) Input High Voltage Vcc x 0.7 Vcc + 0.5 V VOL Output Low Voltage, IOL = +3mA 0.4 V VOH Output High Voltage, VCC = +5V; IOH = -3mA Vcc - 0.8 V or IRQB output signal results, otherwise only the flag is set. Certain instructions clear the interrupt condition (See Figure 21). Clearing an interrupt condition resets the interrupt flag and releases the interrupt output. ABSOLUTE MAXIMUM RATINGS* *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum r ating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C Supply Voltage Limits X5114 5V –10%

Notes: (1) These parameters are periodically sampled and not 100% tested. CAPACITANCE TA = +25°C, VCC = +5V, fSCK = 2.0MHz Notes: (1) This parameter is periodically sampled and not 100% tested. POWER-ON TIMING ADS TU2 TU1 TU0Parameter(1) Typ Typ (Vcc=5V) Max. Error Units Comments 1 1 1 1 Input Port A Threshold Level ADS, TU2-TU0 are bits in the Thresh- old/Block Lock Reg- ister (TBL) 1 1 1 0 Vcc * .8 4.0 –0.1 V 1 1 0 1 Vcc * .7 3.5 –0.1 V 1 1 0 0 Vcc * .6 3.0 –0.1 V 0 x x x Vcc * .5 2.5 –0.1 V 1 0 1 1 Vcc * .4 2.0 –0.1 V 1 0 1 0 Vcc * .3 1.5 –0.1 V 1 0 0 1 Vcc * .2 1.0 –0.1 V 1 0 0 0 Vcc * .1 0.5 –0.1 V Symbol Parameter Max Unit Test Conditions C OUT (1) Output Capacitance 10 pF VOUT = 0V C IN (1) Input Capacitance 6 pF VIN = 0V Symbol Parameter Min Max Unit tRVCC Vcc Rise Time 0.1 V/uS tPOR (1) Power Supply Stable to Issuance of an Instruction without nonvolatile write Cycle1 mS tPOW (1) Power Supply Stable to Issuance of an Instruction with a nonvolatile write Cycle5 mS

A.C. CONDITIONS OF TEST Equivalent A.C. Test Circuits Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 nS Input and Output Timing Levels VCC x 0.5 Output Load Equivalent Output IRQA 920W 100pF Port A 826W 704W 100pF IRQB Port B SO CSC CSO

A.C. CHARACTERISTICS SPI Timing (SPI Clock Mode 3 Only) TA = -40°C to +85°C, Vcc = 4.5V to +5.5V, unless otherwise specified. Notes: (1) This parameter is periodically sampled and not 100% tested. NONVOLATILE WRITE CYCLE TIMING Symbol Parameter Min Max Unit fSCK SPI Clock Frequency 2 MHz tCYC SPI Clock Cycle Time 500 nS tWH SPI Clock High Time 200 nS tWL SPI Clock Low Time 200 nS tLEAD Lead Time 200 nS tLAG Lag Time 400 nS tSU Input Setup Time 50 nS tH Input Hold Time 50 nS tRI (1) Input Rise Time 50 nS tFI (1) Input Fall Time 50 nS tDIS SO Output Disable Time 0 nS tV SO Output Valid Time 100 nS tHO SO Output Hold Time 0 nS tRO (1) SO Output Rise Time 50 nS tFO (1) SO Output Fall Time 50 nS TI SPI Noise Suppression Time Constant 20 nS tCS SPIA_CS or SPIB_CS Deselect Time 100 nS tASU Device Address Setup Time 100 nS tAH Device Address Hold Time 0 nS Symbol Parameter Typ Max Unit tWC Nonvolatile Write Cycle Time 5 10 mS

Hardware Device Address Timing IRQ GENERATION TIMING Symbol Parameter Min Max Unit tIOE Interrupt Output Enable time (Initial error condition valid or Error condi- tion still valid after reset of error flag.) 250 800 nS tFCE Failed Command Enable time (CS HIGH to Failed Command error valid)250 800 nS ... CSa /CSb SCKa/SCKb SIa/SIb MSB LSB tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CSa /CSb SCKa/SCKb SOa/SOb MSB LSB tDIStHOtV ... CSa /CSb tASU tAH (Any Instruction)

C1 C0 Don't Care RIAE or RIBE SCKa/SCKb SIa/SIb tIOEtIOE CSa/CSb Instruction Interrupt condition still exists IRQA , IRQB Failed Instruction tFCE CSa/CSb

Internal (SPI) Read Data From Port A/Port B Internal (SPI) Write Data to Port A/Port B Symbol Parameter Min Max Unit tPSU Port Setup Time 50 nS tPH Port Hold Time 50 nS tPDO Port Data Output Valid Time 100 nS tPSU tPH D0 D7 Don't Care Don't Care Data [7:0] SCKa/SCKb SIa/SIb SOa/SOb Port A/Port B (in) PAL/PBL DataSR Data RP AL/RPBL Instruction tPDO D1 D0 Ne w Port A/Port B Data SCKa/SCKb SIa/SIb SOa/SOb Port A/Port B(out) Data to DVRA/D VRB Old Port A/Port B Data

Single Read input Mode - Parallel Write Data to Port A Symbol Parameter Min Max Unit tPSU Port Setup Time 50 nS tPH Port Hold Time 70 nS tWSTR Write Strobe Time 150 nS tRDRF RDR Full Time 100 nS tRDRE RDR Empty Time 100 nS tRDRP RDR Pulse Time 250 1000 nS tPWRF Port Write RDR Full Time 250 800 nS tPRRE Port Read RDR Empty Time 500 nS tSTRH Strobe High Time 100 nS tSTRL Strobe Low Time 100 nS tWSTR tPSU tPH tRDRF tPWRF Valid Port Data Empty Full TDRE (PB6 out) STRA (PB7 in) Port A Data (in) (interlocked mode) (pulsed mode) IRQA RDR (flag)

Single Read input Mode - SPI Read Data From Port A Multiple Read input Mode - SPI Read Data From Port A tRDRE tRDRE tRDRP tPRRE D0 D6D7 PAL Data Don't Care SR Data RP AL Instruction Full Empty TDRE (PB6 out) SCKa/SCKb SIa/SIb SOa/SOb (interlocked mode) (pulsed mode) IRQA RDR (flag) Don't Care tPSU tPH tSTRH D0 D7 Don't Care Don't Care Data [7:0] SCKa/SCKb SIa/SIb SOa/SOb (1st read) Port A (in) STRB (PB6-out) tSTRL PAL Data —1st read = RPAL Instruction subsequent reads = don’t care subsequent reads = tristate —1st read = SR Data

Output Mode - SPI Write Data to Port A Symbol Parameter Min Max Unit tPV Port Valid Time 150 nS tPR Port Read Time 100 nS tPD Port XRE Disable Time 0 ns tRSTR Read Strobe Pulse 150 nS tXREF XRE Full Time 250 nS tXREE XRE Empty Time 100 nS tXREP XRE Pulse Time 250 1000 nS tPWXF Port Write XRE Full Set Time 500 nS tPRXE Port Read XRE Empty Time 250 800 nS tPV tXREF tXREF tXREP tPWXF Old Port A Data Ne w Port A Data Port A Data Empty Full RDRF (PB5 out) SCKa/SCKb SIa/SIb Ports (Driven Outputs) (interlocked mode) (pulsed mode) IRQA XRE (flag)

Output Mode - Parallel Read Data From Port A BI-DIRECTIONAL TIMING Symbol Parameter Min Max Unit tPSU Port Setup Time 50 nS tPH Port Hold Time 50 nS tPV Port Valid Time 100 nS tRDRF RDR Full Time 100 nS tRDRE RDR Empty Time 100 nS tRDRP RDR Pulse Time 250 1000 nS tPWRF Port Write RDR Full Time 250 800 nS tPRRE Port Read RDR Empty Time 500 nS tXREF XRE Full Time 250 nS tXREE XRE Empty Time 100 nS tXREP XRE Pulse Time 250 1000 nS tPWXF Port Write XRE Full Set Time 500 nS tPRXE Port Read XRE Empty Time 250 800 nS tPEW Port Enable Write Time 150 nS tPEPR Port Read Time 100 nS tPEPD Port XRE Disable Time 0 ns tPEWS R/W Setup Time 20 nS tPEWH R/W Hold Time 0 nS tPER Port Enable Read Time 150 nS tRSTR tPR tPD tXREE tPRXE Valid Port Data Valid Port Data EmptyFull RDRF (PB5 out) STRA (PB7 in) Ports (Driven Outputs) Port A Pins (Tri-State Outputs) (interlocked mode) (pulsed mode) IRQA XRE (flag)

Bi-directional Mode - Parallel Write Data to Port A Bi-directional Mode - SPI Read Data From Port A tPEW tPEWS tPEWH tPSU tPH tRDRF tPWRF Valid Port Data Empty Full TDRE (PB6 out) PEN (PB4 in) R/W (PB7 in) Port A Pins (in) (interlocked mode) (pulsed mode) IRQA RDR (flag) tRDRP tRDRE tRDRE tPRRE PAL Data Full Empty TDRE (PB6 out) SR Data SCKa/SCKb SOa/SOb (interlocked mode) (pulsed mode) IRQA RDR (flag)

Bi-directional Mode - SPI Write Data to Port A Bi-directional Mode - Parallel Read Data From Port A tXREP tPV tXREF tXREF tPWXF Old Port A Data Ne w Port A Data Port A Data Empty Full RDRF (PB5 out) SCKa/SCKb SIa/SIb Ports (Driven Outputs) (interlocked mode) (pulsed mode) IRQA XRE (flag) tPER tPEPR tPEPD tXREE tPRXE Valid Port Data EmptyFull RDRF (PB5 out) PEN (PB4 in) R/W (PB7 in) Port A Pins (out) (interlocked mode) (pulsed mode) IRQA XRE (flag)

CSO Timing (Enable) CSC Timing (Enable) CSO /CSC Timing (Disable) Symbol Parameter Min Max Unit tCSOE Chip Select Output Enable time 200 nS tCSCE Chip Select Cascade Enable time 200 nS tCSOD Chip Select Output Disable time 100 nS tCSCD Chip Select Cascade Disable time 100 nS tCSOE A1 A0 C7 C6 SCKa/SCKb SIa/SIb CSO Device Address CSa/CSb Device Command tCSCE C1 C0 Don't Care Don't Care SCKa/SCKb SIa/SIb CSC NOP Instruction CSa/CSb CSC CSa/CSb CSO tCSOD tCSCD

0.500 (12.70) REF . 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) PIN 1 0.500 (12.70)REF . 0.050 (1.27)REF . 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) 0.021 (0.63) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) 0.032 (0.81) 0.026 (0.66) 0.156 (3.96) 0.145 (3.68) 0.011 (0.28) 0.009 (0.23) 0.180 (4.57) 0.165 (4.19) 0.110 (2.79) 0.100 (2.54) 0.020 (0.51) SEA TING PLANE ±0.004 LEAD CO – PLANARITY 44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J NO TES: 1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONL Y 3926 ILL F29.2

L GA GE PLANE 0.25 C 7°±0°

7052 FM 23

D e b Hd E NO TES: 1.GAGE PLANE DIMENSION IS IN MM. 2.LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM. 48-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L DIM INCHESMILLIMETERS MIN MAX MIN MAX b c D E e Hd He L 0.05 1.35 0.17 0.090

7.0 BSC

9.0 BSC

0.45 0.15 1.45 0.27 0.200 0.75 0.002 0.53 0.007 0.004 0.018 0.006 0.057 0.011 0.008 0.030 1.00TYP 0.039TYP 0.5 BSC 0.02 BSC 3. MOLD FLASH NOT INCLUDED IN DIMENSIONS

0.35 BSC

0.273 BSC

ORDERING INFORMATION

Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package L = 48-Lead TQFP J = 44-Lead PLCC Device X5114 X X LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup- port device or system, or to affect its safety or effectiveness.