X5083V8IZ

X5083_06 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• L o w VCC detection and reset assertion - Four standard reset threshold voltages - Re-program low V CC reset threshold voltage using special programming sequence - Reset signal valid to V CC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock ™ memory - Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array
• Built-in inadvertent write protection - Write enable latch - Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time - 16 byte page write mode - 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages - 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)

Applications

• Communications Equipment - Routers, Hubs, Switches - Set Top Boxes
• Industrial Systems - Process Control - Intelligent Instrumentation
• Computer Systems - Desktop Computers - Network Servers
• Battery Powered Equipment SCK SI VSS WP VCC CS/WDI SO X5083 RESET X5083 CS/WDI WP SO RESET VCC VSS SCK SI Data Sheet June 15, 2006

2 FN8127.3 June 15, 2006 Typical Application Block Diagram uC RESET CS SCK SI SO WP VCC VSS RESET SPI VCC VSS X5083 2.7-5.0V 10K WATCHDOG TIMER COMMAND DECODE & CONTROL LOGIC SI SO SCK CS/WDI VCC POR AND LOW GENERATION VTRIP RESET (X5083)VOLTAGE RESET PROTECT LOGIC 8KBITS EEPROM WATCHDOG DETECTOR WP ARRAY STATUS REGISTER TRANSITION RESET RESET & WATCHDOG TIMEBASE X5083 STANDARD VTRIP LEVEL SUFFIX See “Ordering Information” on page 3 for more details For Custom Settings, call Intersil. X5083

3 FN8127.3 June 15, 2006

Ordering Information

(ACTIVE LOW) PART MARKING V CC RANGE (V) V TRIP RANGE TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # X5083PZ-4.5A (Note) X5083P ZAL 0 to 70 8 Ld PDIP* (Pb-free) MDP0031 X5083PI-4.5A X5083P AM -40 to 85 8 Ld PDIP MDP0031 X5083PIZ-4.5A (Note) X5083P ZAM -40 to 85 8 Ld PDIP* (Pb-free) MDP0031 X5083S8-4.5A X5083 AL 0 to 70 8 Ld SOIC MDP0027 X5083S8Z-4.5A (Note) X5083 ZAL 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5083S8I-4.5A* X5083 AM -40 to 85 8 Ld SOIC MDP0027 X5083S8IZ-4.5A* (Note) X5083 ZAM -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5083V8-4.5A 583 AL 0 to 70 8 Ld TSSOP M8.173 X5083V8Z-4.5A (Note) 583 ZAL 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X5083V8I-4.5A 583 AM -40 to 85 8 Ld TSSOP M8.173 X5083V8IZ-4.5A (Note) 583 ZAM -40 to 85 8 Ld TSSOP (Pb-free) M8.173 X5083P X5083P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP MDP0031 X5083PZ (Note) X5083P Z 0 to 70 8 Ld PDIP* (Pb-free) MDP0031 X5083PI X5083P I -40 to 85 8 Ld PDIP MDP0031 X5083PIZ (Note) X5083P ZI -40 to 85 8 Ld PDIP* (Pb-free) MDP0031 X5083SI X5083 I -40 to 85 8 Ld SOIC MDP0027 X5083S8 X5083 0 to 70 8 Ld SOIC MDP0027 X5083S8Z (Note) X5083 Z 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5083S8I* X5083 I -40 to 85 8 Ld SOIC MDP0027 X5083S8IZ* (Note) X5083 ZI -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5083V8 583 0 to 70 8 Ld TSSOP M8.173 X5083V8Z (Note) 583 Z 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X5083V8I 583 I -40 to 85 8 Ld TSSOP M8.173 X5083V8IZ (Note) 583 IZ -40 to 85 8 Ld TSSOP (Pb-free) M8.173 X5083PZ-2.7A (Note) X5083P ZAN 0 to 70 8 Ld PDIP* (Pb-free) MDP0031 X5083PI-2.7A X5083P AP -40 to 85 8 Ld PDIP MDP0031 X5083PIZ-2.7A (Note) X5083P ZAP -40 to 85 8 Ld PDIP* (Pb-free) MDP0031 X5083S8-2.7A X5083 AN 0 to 70 8 Ld SOIC MDP0027 X5083S8Z-2.7A (Note) X5083 ZAN 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5083S8I-2.7A X5083 AP -40 to 85 8 Ld SOIC MDP0027 X5083S8IZ-2.7A* (Note) X5083 ZAP -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5083V8-2.7A 583 AN 0 to 70 8 Ld TSSOP M8.173 X5083V8Z-2.7A (Note) 583 ZAN 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X5083V8I-2.7A 583 AP -40 to 85 8 Ld TSSOP M8.173 X5083V8IZ-2.7A (Note) 583 ZAP -40 to 85 8 Ld TSSOP (Pb-free) M8.173 X5083

4 FN8127.3 June 15, 2006 Pin Description X5083PZ-2.7 (Note) X5083P ZF 0 to 70 8 Ld PDIP* (Pb-free) MDP0031 X5083PI-2.7 X5083P G -40 to 85 8 Ld PDIP MDP0031 X5083PIZ-2.7 (Note) X5083P ZG -40 to 85 8 Ld PDIP* (Pb-free) MDP0031 X5083S8-2.7* X5083 F 0 to 70 8 Ld SOIC MDP0027 X5083S8Z-2.7* (Note) X5083 ZF 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X5083S8I-2.7* X5083 G -40 to 85 8 Ld SOIC MDP0027 X5083S8IZ-2.7* (Note) X5083 ZG -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X5083V8-2.7 583 F 0 to 70 8 Ld TSSOP M8.173 X5083V8Z-2.7 (Note) 583 FZ 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X5083V8I-2.7 583G -40 to 85 8 Ld TSSOP M8.173 X5083V8IZ-2.7 (Note) 583 GZ -40 to 85 8 Ld TSSOP (Pb-free) M8.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T1" suffix for tape and reel. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING V CC RANGE (V) V TRIP RANGE TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # PIN (SOIC/ PDIP) PIN TSSOP NAME FUNCTION 13 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is und erway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET going active. 24 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 57 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 68 S C K Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 35 W P Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.

46 V SS Ground

82 V CC Supply Voltage

7 1 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power-up at about 1V and remains active for 250ms after the power supply stabilizes. X5083

5 FN8127.3 June 15, 2006 Principles of Operation Power-on Reset Application of power to the X5083 activates a power-on reset circuit. This circuit goes LOW at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. RESET active also blocks communication to the device through the SPI interface. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. While VCC < VTRIP communications to the device are inhibited. Low Voltage Monitoring During operation, the X5083 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition and terminates any SPI communication in progress. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. When VCC falls below VTRIP, any communications in progress are terminated and communications are inhibited until V CC exceeds VTRIP for tPURST. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS /WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits with no action taken by the microprocessor these bits remain unchanged, even after total power failure. VCC Threshold Reset Procedure The X5083 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard V TRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5083 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new V TRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the new V TRIP voltage, apply the desired VTRIP threshold voltage to the Vcc pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h. X5083

16 Bits

FIGURE 1. SET V TRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE) FIGURE 2. RESET V TRIP LEVEL SEQUENCE (VCC > 3V. WP = 15-18V) FIGURE 3. SAMPLE V TRIP RESET CIRCUIT

FIGURE 4. V TRIP PROGRAMMING SEQUENCE

operation on a simple four-wire bus. minimum data retention of 100 years. popular microcontroller families. The RDSR instruction provides access to the status register. write cycle. The status register is formatted as follows. instruction to the device as described in Table 1 and Figure 9. written until block lock is removed or changed. TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION

1 WD2000 --->no block lock: 00h-00h--->none of the array

command (read or write) or cycling the power to the device. transmitted to the device, followed by the 16-bit address. the next higher address after each byte of data is shifted out. select the device followed by the 8-bit RDSR instruction. register sequence (Figure 6). may have been previously written. time, the write operation will not be completed (Figure 8). timer bits set the operation of the watchdog timer (Table 2). the Status Register Contents. See Figure 10. watchdog timer has reached its programmable time out limit.

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• Reset signal is active for t PURST.

TABLE 2. WATCHDOG TIMER DEFINITION

FIGURE 10. READ NONVOLATILE WRITE STATUS

FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)

14 FN8127.3 June 15, 2006 Absolute Maximum Ratings Operating Conditions Temperature Range VCC Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP MAX ICC1 VCC Write Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 5m A ICC2 VCC Read Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 0.4 mA ISB1 VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC = 5.5V 1µ A ISB2 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA ISB3 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC = 3.6V 20 µA ILI Input Leakage Current V IN = VSS to VCC 0.1 10 µA ILO Output Leakage Current V OUT = VSS to VCC 0.1 10 µA VIL (Note 1) Input LOW Voltage -0.5 V CC x 0.3 V VIH (Note 1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage V CC > 3.3V, IOL = 2.1mA 0.4 V VOL2 Output LOW Voltage 2V < V CC ≤ 3.3V, IOL = 1mA 0.4 V VOL3 Output LOW Voltage V CC ≤ 2V, IOL = 0.5mA 0.4 V VOH1 Output HIGH Voltage V CC > 3.3V, IOH = -1.0mA V CC - 0.8 V VOH2 Output HIGH Voltage 2V < V CC ≤ 3.3V, IOH = -0.4mA V CC - 0.4 V VOH3 Output HIGH Voltage V CC ≤ 2V, IOH = -0.25mA V CC - 0.2 V VOLRS Reset Output LOW Voltage I OL = 1mA 0.4 V Power-Up Timing SYMBOL PARAMETER MIN MAX UNIT tPUR (Note 2) Power-up to read operation 1 ms tPUW (Note 2) Power-up to write operation 5 ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST MAX UNIT CONDITIONS COUT (Note 2) Output capacitance (SO, RESET , RESET) 8 pF V OUT = 0V CIN (Note 2) Input capacitance (SCK, SI, CS , WP)6 p F V IN = 0V NOTES: 1. V IL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. X5083

15 FN8127.3 June 15, 2006 Equivalent A.C. Load Circuit at 5V VCC SO 100pF 3.3kΩ RESET 30pF 1.64kΩ 1.64kΩ OUTPUT A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 SYMBOL PARAMETER 2.7V-5.5V UNITMIN MAX DATA INPUT TIMING fSCK Clock frequency 0 3.3 MHz tCYC Cycle time 300 ns tLEAD CS lead time 150 ns tLAG CS lag time 150 ns tWH Clock HIGH time 130 ns tWL Clock LOW time 130 ns tSU Data setup time 20 ns tH Data hold time 20 ns tRI (Note 3) Input rise time 2µ s tFI (Note 3) Input fall time 2µ s tCS CS deselect time 100 ns tWC (Note 4) Write cycle time 10 ms DATA OUTPUT TIMING fSCK Clock frequency 0 3.3 MHz tDIS Output disable time 150 ns tV Output valid from clock low 130 ns tHO Output hold time 0 ns tRO (Note 3) Output rise time 50 ns tFO (Note 3) Output fall time 50 ns NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. X5083

16 FN8127.3 June 15, 2006 Serial Output Timing Serial Input Timing Power-Up and Power-Down Timing SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance VCC tPURST tPURST tR tF tRPD RESET

0 Volts

17 FN8127.3 June 15, 2006 CS vs. RESET Timing RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT VTRIP Reset trip point voltage, X5083PT-4.5A (Note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.00 2.7 V t PURST Power-up reset time out 100 200 280 ms tRPD (Note 5) V CC detect to reset/output 500 ns tF (Note 5) V CC fall time 0.1 ns tR (Note 5) V CC rise time 0.1 ns VRVALID Reset valid VCC 1V NOTES: 5. This parameter is periodically sampled and not 100% tested. 6. PT = Package/Temperature CS tCST RESET tWDO tRST tWDO tRST RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog time out period, WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 200 600 1.4 300 800 ms ms sec t CST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 300 ms X5083

18 FN8127.3 June 15, 2006 VTRIP Programming Timing Diagram SCK SI CS 0001h (set) VCC (VTRIP) VPE tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 02h06h 0003h (reset)WREN Write Addr. Data VTRIP Programming Parameters PARAMETER DESCRIPTION MIN MAX UNIT tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1µ s tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tVPO VTRIP program enable voltage off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 2.0 5.0 V Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV NOTES: 7. V TRIP programming parameters are periodically sampled and are not 100% tested. 8. For custom V TRIP settings, Contact Factory. X5083

19 FN8127.3 June 15, 2006 X5083 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

20 FN8127.3 June 15, 2006 X5083 Plastic Dual-In-Line Packages (PDIP) NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the l eads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES N 8 14 16 18 20 Reference Rev. B 2/99 D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8127.3 June 15, 2006 X5083 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7 α 0o 8o 0o 8o - Rev. 1 12/00