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Technical content

Features

  • L o w VCC detection and reset assertion - Four standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V
  • Selectable time out watchdog timer
  • Long battery life with low power consumption - <50µA max standby current, watchdog on - <1µA max standby current, watchdog off - <400µA max active current during read
  • 8Kbits of EEPROM
  • Save critical data with Block Lock ™ memory - Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array
  • Built-in inadvertent write protection - Write enable latch - Write protect pin
  • SPI Interface - 3.3MHz clock rate
  • Minimize programming time - 16 byte page write mode - 5ms write cycle time (typical)
  • SPI modes (0,0 & 1,1)
  • Available packages - 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
  • Pb-free plus anneal available (RoHS compliant)

Applications

  • Communications Equipment - Routers, Hubs, Switches - Set Top Boxes
  • Industrial Systems - Process Control - Intelligent Instrumentation
  • Computer Systems - Desktop Computers - Network Servers
  • Battery Powered Equipment SCK SI VSS WP VCC CS/WDI SO X5083 RESET NO LONGER AVAILABLE OR SUPPORTED X5083 CS/WDI WP SO RESET VCC VSS SCK SI

FN8127 Rev 4.00 Page 2 of 21 November 12, 2015 Typical Application Block Diagram uC RESET CS SCK SI SO WP VCC VSS RESET SPI VCC VSS X5083 2.7-5.0V 10K WATCHDOG TIMER COMMAND DECODE & CONTROL LOGIC SI SO SCK CS/WDI VCC POR AND LOW GENERATION VTRIP RESET (X5083)VOLTAGE RESET PROTECT LOGIC 8KBITS EEPROM WATCHDOG DETECTOR WP ARRAY STATUS REGISTER TRANSITION RESET RESET & WATCHDOG TIMEBASE X5083 STANDARD VTRIP LEVEL SUFFIX See “Ordering Information” on page 3 for more details For Custom Settings, call Intersil.

FN8127 Rev 4.00 Page 3 of 21 November 12, 2015 Pin Description

Ordering Information

PART NUMBER RESET (ACTIVE LOW) (Note 1) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # X5083PIZ-4.5A (No longer available or supported) X5083P ZAM 4.5-5.5 4.5-4.75 -40 to 85 8 Ld PDIP* MDP0031 X5083S8Z-4.5A X5083 ZAL 0 to 70 8 Ld SOIC M8.15E X5083S8IZ-4.5A (Note 2) X5083 ZAM -40 to 85 8 Ld SOIC M8.15E X5083S8Z X5083 Z 4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC M8.15E X5083S8IZ (Note 2) X5083 ZI -40 to 85 8 Ld SOIC M8.15E X5083V8IZ (No longer available, recommended replacement: X5083S8IZ) 583 IZ -40 to 85 8 Ld TSSOP M8.173 X5083S8IZ-2.7A* X5083 ZAP -40 to 85 8 Ld SOIC M8.15E X5083S8Z-2.7* X5083 ZF 2.7-5.5 2.55-2.7 0 to 70 8 Ld SOIC M8.15E X5083S8IZ-2.7* X5083 ZG -40 to 85 8 Ld SOIC M8.15E X5083V8IZ-2.7 (No longer available, recommended replacement: X5083S8IZ-2.7) 583 GZ -40 to 85 8 Ld TSSOP M8.173 NOTE: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. *Add "-T1" suffix for tape and reel. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. PIN (SOIC/ PDIP) PIN TSSOP NAME FUNCTION 13 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycl e is underway, the d evice will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results i n RESET going active. 24 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 57 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 68 S C K Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 35 W P Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.

46 V SS Ground

82 V CC Supply Voltage

7 1 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power-up at about 1V and remains active for 250ms after the power supply stabilizes.

active until VCC returns and exceeds VTRIP for 200ms. bits in the status register determine the watchdog timer period. unchanged, even after total power failure. application of a high voltage control signal. necessary to reset the trip point before setting the new value. sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h. procedure must be used to set the voltage to a lower value. sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h.

16 Bits

FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE)

FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15-18V) FIGURE 3. SAMPLE VTRIP RESET CIRCUIT

FIGURE 4. VTRIP PROGRAMMING SEQUENCE

minimum data retention of 100 years. SCK. CS must be LOW during the entire operation. The RDSR instruction provides access to the status register. write cycle. The status register is formatted as follows. vary in size from one page to as much as half of the entire array. TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION

command. Then wait 10ms and do a read status command. memory at the selected address is shifted out on the SO line. read EEPROM array sequence (Figure 5). have been previously written. write operation will not be completed (Figure 8). reserved and will return ’0’ when read. See Figure 6. timer has reached its programmable time out limit.

  • The device is in the low power standby state.
  • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
  • SO pin is high impedance.
  • The write enable latch is reset.
  • Reset signal is active for tPURST.

TABLE 2. WATCHDOG TIMER DEFINITION

FIGURE 10. READ NONVOLATILE WRITE STATUS

FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)

FN8127 Rev 4.00 Page 13 of 21 November 12, 2015 Absolute Maximum Ratings Operating Conditions Temperature Range VCC Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP MAX ICC1 VCC Write Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 5m A ICC2 VCC Read Current (Active) SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 0.4 mA ISB1 VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC = 5.5V 1µ A ISB2 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA ISB3 VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC = 3.6V 20 µA ILI Input Leakage Current V IN = VSS to VCC 0 . 1 1 0 µ A ILO Output Leakage Current V OUT = VSS to VCC 0.1 10 µA VIL (Note 1) Input LOW Voltage -0.5 V CC x 0.3 V VIH (Note 1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage V CC > 3.3V, IOL = 2.1mA 0.4 V VOL2 Output LOW Voltage 2V < V CC  3.3V, IOL = 1mA 0.4 V VOL3 Output LOW Voltage V CC  2V, IOL = 0.5mA 0.4 V VOH1 Output HIGH Voltage V CC > 3.3V, IOH = -1.0mA V CC - 0.8 V VOH2 Output HIGH Voltage 2V < V CC  3.3V, IOH = -0.4mA V CC - 0.4 V VOH3 Output HIGH Voltage V CC  2V, IOH = -0.25mA V CC - 0.2 V VOLRS Reset Output LOW Voltage I OL = 1mA 0.4 V Power-Up Timing SYMBOL PARAMETER MIN MAX UNIT tPUR (Note 2) Power-up to read operation 1 ms tPUW (Note 2) Power-up to write operation 5 ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST MAX UNIT CONDITIONS COUT (Note 2) Output capacitance (SO, RESET, RESET) 8 pF V OUT = 0V CIN (Note 2) Input capacitance (SCK, SI, CS , WP)6 p F V IN = 0V NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.

FN8127 Rev 4.00 Page 14 of 21 November 12, 2015 Equivalent A.C. Load Circuit at 5V VCC SO 100pF 3.3k RESET 30pF 1.64k 1.64k OUTPUT A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 SYMBOL PARAMETER 2.7V-5.5V UNITMIN MAX DATA INPUT TIMING fSCK Clock frequency 0 3.3 MHz tCYC Cycle time 300 ns tLEAD CS lead time 150 ns tLAG CS lag time 150 ns tWH Clock HIGH time 130 ns tWL Clock LOW time 130 ns tSU Data setup time 20 ns tH Data hold time 20 ns tRI (Note 3) Input rise time 2µ s tFI (Note 3) Input fall time 2µ s tCS CS deselect time 100 ns tWC (Note 4) Write cycle time 10 ms DATA OUTPUT TIMING fSCK Clock frequency 0 3.3 MHz tDIS Output disable time 150 ns tV Output valid from clock low 130 ns tHO Output hold time 0 ns tRO (Note 3) Output rise time 50 ns tFO (Note 3) Output fall time 50 ns NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

FN8127 Rev 4.00 Page 15 of 21 November 12, 2015 Serial Output Timing Serial Input Timing Power-Up and Power-Down Timing SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance VCC tPURST tPURST tR tF tRPD RESET

0 Volts

FN8127 Rev 4.00 Page 16 of 21 November 12, 2015 CS vs. RESET Timing RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT VTRIP Reset trip point voltage, X5083PT-4.5A (Note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.00 2.7 V t PURST Power-up reset time out 100 200 280 ms tRPD (Note 5) V CC detect to reset/output 500 ns tF (Note 5) V CC fall time 0.1 ns tR (Note 5) V CC rise time 0.1 ns VRVALID Reset valid VCC 1V NOTES: 5. This parameter is periodically sampled and not 100% tested. 6. PT = Package/Temperature CS tCST RESET tWDO tRST tWDO tRST RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog time out period, WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 200 600 1.4 300 800 ms ms sec t CST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 300 ms

FN8127 Rev 4.00 Page 17 of 21 November 12, 2015 VTRIP Programming Timing Diagram SCK SI CS 0001h (set) VCC (VTRIP) VPE tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 02h06h 0003h (reset)WREN Write Addr. Data VTRIP Programming Parameters PARAMETER DESCRIPTION MIN MAX UNIT tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1µ s tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tVPO VTRIP program enable voltage off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 2.0 5.0 V Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV NOTES: 7. VTRIP programming parameters are periodically sampled and are not 100% tested. 8. For custom VTRIP settings, Contact Factory.

FN8127 Rev 4.00 Page 18 of 21 November 12, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE November 12, 2015 FN8127.4 Updated Ordering Information table on page 3. Added Revision History and About Intersil sections. Updated POD MDP0027 to POD M8.15E.

FN8127 Rev 4.00 Page 19 of 21 November 12, 2015 Package Outline Drawing M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09 Unless otherwise specified, tolerance : Decimal ± 0.05 The pin #1 identifier may be either a mold or mark feature. Interlead flash or protrusions shall not exceed 0.25mm per side. Dimension does not include interlead flash or protrusions. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Dimensions are in millimeters.1. NOTES: DETAIL "A" SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN TOP VIEW A B

0.25 AMC B

C 0.10 C ID MARK PIN NO.1 (0.35) x 45° SEATING PLANE GAUGE PLANE 0.25 (5.40) (1.50) 4.90 ± 0.10 3.90 ± 0.10 1.27 0.43 ± 0.076 0.63 ±0.23 4° ± 4° DETAIL "A" 0.22 ± 0.03 0.175 ± 0.075 1.45 ± 0.1

1.75 MAX

(1.27) (0.60) 6.0 ± 0.20 Reference to JEDEC MS-012.6. SIDE VIEW “B”

FN8127 Rev 4.00 Page 20 of 21 November 12, 2015 Plastic Dual-In-Line Packages (PDIP) NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the l eads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES N 8 14 16 18 20 Reference Rev. B 2/99 D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c

FN8127 Rev 4.00 Page 21 of 21 November 12, 2015 X5083 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7  0o 8o 0o 8o - Rev. 1 12/00