X5083V8-2.7

X5083 XICOR | Alldatasheet

Document overview

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Technical content

REV 1.1.6 6/25/02 Characteristics subject to change without notice. 1 of 21 www.xicor.com X5083 CPU Supervisor with 8Kbit SPI EEPROM

FEATURES

• Low V CC detection and reset assertion —Four standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence. —Reset signal valid to V CC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off —<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock memory —Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array
• Built-in inadvertent write protection —Write enable latch —Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time —16 byte page write mode —5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages —8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP

APPLICATIONS

• Communications Equipment —Routers, Hubs, Switches —Set Top Boxes
• Industrial Systems —Process Control —Intelligent Instrumentation
• Computer Systems —Desktop Computers —Network Servers
• Battery Powered Equipment uC RESET CS SCK SI SO WP VCC VSS RESET SPI VCC VSS X5083 Typical Application 2.7-5.0V 10K BLOCK DIAGRAM Watchdog Timer Command Decode & Control Logic SI SO SCK CS /WDI VCC POR and Low Generation VTRIP RESET (X5083)Voltage Reset Protect Logic 8Kbits EEPROM Watchdog Detector WP Array Status Register Transition Reset Reset & Watchdog Timebase X5083 Standard VTRIP Level Suffix See “Ordering Information” on page 21 for more details For Custom Settings, call Xicor.

Characteristics subject to change without notice. 2 of 21REV 1.1.6 6/25/02 www.xicor.com

DESCRIPTION

This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Super- vision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to sta- bilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET is asserted until V CC returns to the proper operating level and stabilizes. Five industry standard V TRIP thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. PIN CONFIGURATION PIN DESCRIPTION Pin (SOIC/ PDIP) Pin TSSOP Name Function

13 C S /WDI

Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET going active.

24 S O

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 57S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 6 8 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

35 W P

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the device operates normally. 46 V SS Ground 82 V CC Supply Voltage 7 1 RESET Reset Output . RESET is an active LOW, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 250ms. RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about 1V and remains active for 250ms after the power supply stabilizes. SCK SI VSS WP VCC CS /WDI SO 8-Lead TSSOP X5083 RESET 8-Lead SOIC, PDIP X5083 CS /WDI WP SO RESET VCC VSS SCK SI

Characteristics subject to change without notice. cient voltage or prior to stabilization of the oscillator. unchanged, even after total power failure. point before setting the new value. mand, followed by a write of Data 00h to address 01h. Figure 1. Set V

16 Bits

Characteristics subject to change without notice. set the voltage to a lower value. Figure 2. Reset V Figure 3. Sample V

Characteristics subject to change without notice. Figure 4. V allowing operation on a simple four-wire bus. and a minimum data retention of 100 years. popular microcontroller families. supply voltage falls below a preset minimum VTRIP.

after the completion of a valid Write Cycle. but not written until block lock is removed or changed. Table 1. Instruction Set and Block Lock Protection Byte Definition

1 WD 2000 --->no block lock: 00h-00h --->none of the array

WREN, followed by a write status register command. Then wait 10ms and do a read status command. Table 2. Watchdog Timer Definition

When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequen- tially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 5). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 6). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the same page and overwrite any data that may have been previously written. For a write operation (byte or page write) to be com- pleted, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 5, 6 and 7 must be “0”. Read Status Operation If there is not a nonvolatile write in progress, the read status instruction returns the block lock setting from the status register which contains the watchdog timer bits WD1, WD0, and the block lock bits IDL2-IDL0 (Figure 6). The block lock bits define the block lock condition (Table 1). The watchdog timer bits set the operation of the watchdog timer (Table 2). The other bits are reserved and will return ’0’ when read. See Figure 6. During an internal nonvolatile write operaiton, the Read Status Instruction returns a HIGH on SO in the first bit following the RDSR instruction (the MSB). The remaining bits in the output status byte are undefined. Repeated Read Status Instructions return the MSB as a ‘1’ until the nonvolatile write cycle is complete. When the nonvolatile write cycle is completed, the RDSR instruction returns a ‘0’ in the MSB position with the remaining bits of the status register undefined. Subse- quent RDSR instructions return the Status Register Contents. See Figure 10. RESET Operation The RESET output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The write enable latch is reset. – Reset signal is active for t PURST . Data Protection The following circuitry has been included to prevent inadvertent writes: – A WREN instruction must be issued to set the write enable latch. –C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle. – When VCC is below VTRIP, communications to the device are inhibited.

Figure 10. Read Nonvolatile Write Status

Figure 11. End of Nonvolatile Write (no Polling)

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Voltage Option Limits –2.7 2.7V to 5.5V Blank 4.5V-5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Unit Test ConditionsMin. Typ. Max. ICC1 VCC write current (active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ICC2 VCC read current (active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ISB1 VCC standby current WDT = OFF 1µ A C S = VCC , VIN = VSS or VCC , VCC = 5.5V ISB2 VCC standby current WDT = ON 50 µA CS = VCC , VIN = VSS or VCC , VCC = 5.5V ISB3 VCC standby current WDT = ON 20 µA CS = VCC , VIN = VSS or VCC , VCC = 3.6V ILI Input leakage current 0.1 10 µA V IN = VSS to VCC ILO Output leakage current 0.1 10 µA V OUT = VSS to VCC VIL (1) Input LOW voltage –0.5 V CC x 0.3 V VIH (1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < V CC ≤ 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V V CC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH voltage V CC – 0.8 V V CC > 3.3V, IOH = –1.0mA VOH2 Output HIGH voltage V CC – 0.4 V 2V < V CC ≤ 3.3V, IOH = –0.4mA VOH3 Output HIGH voltage V CC – 0.2 V V CC ≤ 2V, IOH = –0.25mA VOLRS Reset output LOW voltage 0.4 V I OL = 1mA

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. Symbol Parameter Min. Max. Unit tPUR (2) Power-up to read operation 1 ms tPUW (2) Power-up to write operation 5 ms Symbol Test Max. Unit Conditions C OUT (2) Output capacitance (SO, RESET, RESET) 8 pF V OUT = 0V C IN (2) Input capacitance (SCK, SI, CS, WP) 6 pF V IN = 0V EQUIVALENT A.C. LOAD CIRCUIT AT 5V V CC A.C. TEST CONDITIONS SO 100pF 3.3KΩ RESET 30pF 1.64KΩ 1.64KΩ Output Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter 2.7V–5.5V UnitMin. Max. fSCK Clock frequency 0 3.3 MHz tCYC Cycle time 300 ns tLEAD CS lead time 150 ns tLAG CS lag time 150 ns tWH Clock HIGH time 130 ns tWL Clock LOW time 130 ns tSU Data setup time 20 ns tH Data hold time 20 ns tRI (3) Input rise time 2 µs tFI (3) Input fall time 2 µs tCS CS deselect time 100 ns tWC (4) Write cycle time 10 ms

Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Serial Input Timing Symbol Parameter 2.7V–5.5V Unit Min. Max. fSCK Clock frequency 0 3.3 MHz tDIS Output disable time 150 ns tV Output valid from clock low 130 ns tHO Output hold time 0 ns tRO (3) Output rise time 50 ns tFO (3) Output fall time 50 ns SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI High Impedance

Power-Up and Power-Down Timing RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. (6) PT= Package/Temperature CS vs. RESET Timing RESET Output Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5083PT-4.5A (See note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.00 2.7 V t PURST Power-up reset time out 100 200 280 ms tRPD (5) VCC detect to reset/output 500 ns tF (5) VCC fall time 0.1 ns tR (5) VCC rise time 0.1 ns VRVALID Reset valid VCC 1V Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog time out period, WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 200 600 1.4 300 800 ms ms sec t CST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 300 ms VCC tPURST tPURST tR tF tRPD RESET

0 Volts

VTRIP Programming Timing Diagram VTRIP Programming Parameters Parameter Description Min. Max. Unit tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1 µs tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tVPO VTRIP program enable voltage off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 2.0 5.0 V Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV Note 1: VTRIP programming parameters are periodically sampled and are not 100% tested. Note 2: For custom VTRIP settings, Contact Factory. SCK SI CS 0001h (set) VCC (VTRIP) VPE tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 02h06h 0003h (reset)WREN Write Addr. Data

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16)(7.72) (1.78) (0.42) (0.65) All Measurements Are Typical

Ordering Information

VCC Range V TRIP Range Package Operating Temperature Range Part Number RESET (Active LOW) 8L SOIC 0–70°C X5083S8-4.5A -40–85°C X5083S8I-4.5A 8L SOIC 0–70°C X5083S8 -40–85°C X5083S8I 8L TSSOP 0–70°C X5083V8 -40–85°C X5083S8I-2.7A 8L TSSOP 0–70°C X5083V8-2.7A -40–85°C X5083S8I-2.7 8L TSSOP 0–70°C X5083V8-2.7 8-Lead TSSOP EYWW XXXXX 583F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V 583G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V X583 = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V 583I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V 8-Lead SOIC/PDIP X5083X XX F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V 583AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V 583AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V 583AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V 583AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V YWW = year/work week device is packaged.

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2002 Patents Pending