X5043V14I

X5043 XICOR | Alldatasheet

Document overview

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Technical content

REV 1.1.2 5/29/01 Characteristics subject to change without notice. 1 of 20 www.xicor.com X5043/X5045 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM

FEATURES

• Selectable time out watchdog timer
• L o w V CC detection and reset assertion —Five standard reset threshold voltages —Re-program low V CC reset threshold voltage using special programming sequence. —Reset signal valid to V CC = 1V
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<10µA max standby current, watchdog off —<2mA max active current during read
• 2.7V to 5.5V and 4.5V to 5.5V power supply versions
• 4Kbits of EEPROM–1M write cycle endurance
• Save critical data with Block Lock memory —Protect 1/4, 1/2, all or none of EEPROM array
• Built-in inadvertent write protection —Write enable latch —Write protect pin
• 3.3MHz clock rate
• Minimize programming time —16-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages —8-lead MSOP, 8-lead SOIC, 8-pin PDIP —14-lead TSSOP

DESCRIPTION

These devices combine four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscil- lator to stabilize before the processor executes code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Five industry standard V TRIP thresholds are available, however, Xicor’s unique circuits allow the threshold to be repro- grammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SI SO SCK CS /WDI VCC Reset & Watchdog Timebase Power on and GenerationVTRIP RESET /RESET Reset Low Voltage Status Register Protect Logic 1Kbits 1Kbits 2Kbits EEPROM Array Watchdog Transition Detector WP X5043 = RESET X5045 = RESET VCC Threshold Reset Logic

Characteristics subject to change without notice. 2 of 20REV 1.1.2 5/29/01 www.xicor.com The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software proto- col allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the fall- ing edge of the clock input. Chip Select (CS When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non vol- atile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET /RESET is an active low/HIGH, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A fall- ing edge of CS will reset the watchdog timer. PIN NAMES 8-Lead SOIC/PDIP/MSOP CS /WDI WP SO RESET /RESET VCC X5043/45 VSS SCK SI 14-Lead TSSOP CS NC SO RESET /RESET VCC X5043/45NC NC NC WP NC 5 7VSS NC10 SCK SI Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input V SS Ground V CC Supply Voltage RESET /RESET Reset Output

Characteristics subject to change without notice. ficient voltage or prior to stabilization of the oscillator. the processor to begin executing code. signal remains active until the voltage drops below 1V. remain unchanged, even during total power failure. the application of a high voltage control signal. point before setting the new value. mand, followed by a write of Data 00h to address 01h. This operation also writes 00h to array address 01h. Figure 1. Set V

8 Bits

Characteristics subject to change without notice. set the voltage to a lower value. Bring WP LOW to complete the operation. Figure 2. Reset V Figure 3. Sample V

Characteristics subject to change without notice. Figure 4. V protocol allowing operation on a simple four-wire bus. cycles and a minimum data retention of 100 years. popular microcontroller families. LOW during the entire operation. Table 1. Instruction Set Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

is not necessary to send a byte address or data. Figure 5. Write Enable/Disable Latch Sequence “0”, no write is in progress. WEL bit and the WRDS instruction resets the WEL bit. protection of that portion of memory. programmed with the WRSR instruction. may be read at any time, even during a Write Cycle. enter the WRSR instruction followed by 8 bits of data. WRSR, the WRSR instruction is ignored.

Figure 8. Read EEPROM Array Sequence data that has been previously written. not be completed (Figure 9). the nonvolatile write is in progress.

Figure 9. Write Memory Sequence – The device is in the low power standby state. an active state and receive an instruction. – The Write Enable Latch is reset. order to start a nonvolatile write cycle. protection for the memory array. – The WP pin LOW blocks nonvolatile write operations.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Option Supply Voltage Limits Blank, -4.5A 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) SCK frequency measured from V CC x 0.1/VCC x 0.9 Symbol Parameter Limits Unit Test Conditions/CommentsMin. Typ. (2) Max. ICC1 VCC Write Current (Active) 3 mA SCK = 3.3MHz (3); SO, RESET, RESET = Open ICC2 VCC Read Current (Active) 2 mA SCK = 3.3MHz (3); SI = VSS , RESET, RESET = Open ISB1 VCC Standby Current WDT = OFF 10 µA CS = VCC , SCK, SI = VSS , VCC = 5.5V ISB2 VCC Standby Current WDT = ON 50 µA CS = VCC , SCK, SI = VSS , VCC = 5.5V ILI Input Leakage Current 0.1 10 µA SCK, SI, WP = V SS to VCC ILO Output Leakage Current 0.1 10 µA SO, RESET , RESET = VSS to VCC VIL (1) Input LOW Voltage –0.5 V CC x 0.3 V SCK, SI, WP , CS VIH (1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V SCK, SI, WP , CS VOL Output LOW Voltage (SO) 0.4 V I OL = 2mA @ VCC = 2.7V IOL = 0.5mA @ VCC = 1.8V VOH1 Output HIGH Voltage (SO) VCC – 0.8 V V CC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage (SO) VCC – 0.4 V 2V < V CC ≤ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage (SO) VCC – 0.2 V V CC ≤ 2V, IOH = –0.25mA VOLRS Output LOW Voltage (RESET , RESET)

0.4 V I OL = 1mA

Symbol Test Max. Unit Conditions C OUT (2) Output Capacitance (SO, RESET, RESET) 8 pF V OUT = 0V C IN (2) Input Capacitance (SCK, SI, CS, WP) 6 pF V IN = 0V

Equivalent A.C. Load Circuit at 5V VCC A.C. Test Conditions Output 30pF 4.6KΩ RESET/RESET 30pF 1.64KΩ 1.64KΩ Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Data Output Timing Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter 2.7V–5.5V UnitMin. Max. fSCK Clock Frequency 0 3.3 MHz tCYC Cycle Time 300 ns tLEAD CS Lead Time 150 ns tLAG CS Lag Time 150 ns tWH Clock HIGH Time 130 ns tWL Clock LOW Time 130 ns tSU Data Setup Time 30 ns tH Data Hold Time 30 ns tRI (3) Input Rise Time 2 µs tFI (3) Input Fall Time 2 µs tCS CS Deselect Time 100 ns tWC (4) Write Cycle Time 10 ms Symbol Parameter 2.7–5.5V Unit Min. Max. fSCK Clock Frequency 0 3.3 MHz tDIS Output Disable Time 150 ns tV Output Valid from Clock Low 120 ns tHO Output Hold Time 0 ns tRO (3) Output Rise Time 50 ns tFO (3) Output Fall Time 50 ns

MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB In tSU tRI tLAGtLEAD tH LSB In tCS tFI High Impedance WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

Power-Up and Power-Down Timing RESET Output Timing Note: (5) This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing RESET /RESET Output Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V t PURST Power-up Reset Time Out 100 200 400 ms tRPD (5) VCC Detect to Reset/Output 500 ns tF (5) VCC Fall Time 10 µs tR (5) VCC Rise Time 0.1 ns VRVALID Reset Valid VCC 1V Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time Out 100 200 400 ms VCC tPURST tF tRPD RESET (X5043)

0 Volts

RESET (X5045) VTRIP tPURST tR CS /WDI tCST RESET RESET tWDO tRSTtWDO tRST

VTRIP Programming Timing Diagram VTRIP Programming Parameters Parameter Description Min Max Unit tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tPCS VTRIP Programming CS inactive time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied–VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied–Vta1)–VTRIP. Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0–75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. SCK SI CS 01h or VCC (VTRIP) WP tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 02h 06h 03h

0.118 ± 0.002 (3.00 ± 0.05) 0.040 ± 0.002 (1.02 ± 0.05) 0.150 (3.81) Ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7° Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 8-Lead Miniature Small Outline Gull Wing Package Type M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 0.220" 0.0256" Typical 0.025" Typical 0.020" Typical

8 PlacesFOOTPRINT

Ref.

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) 8L SOIC -40°C–85°C X5043S8I-4.5A X5045S8I-4.5A 8L MSOP -40°C–85°C X5043M8I-4.5A X5045M8I-4.5A 14L TSSOP -40°C–85°C X5043V14I-4.5A X5045V14I-4.5A 4.25-4.5 8-Pin PDIP -40°C–85°C X5043PI X5045PI 8L SOIC 0°C–70°C X5043S8 X5045S8 -40°C–85°C X5043S8I X5045S8I 8L MSOP -40°C–85°C X5043M8I X5045M8I 14L TSSOP -40°C–85°C X5043V14I X5045V14I 8L SOIC -40°C–85°C X5043S8I-2.7A X5045S8I-2.7A 8L MSOP -40°C–85°C X5043M8I-2.7A X5045M8I-2.7A 14L TSSOP -40°C–85°C X5043V14I-2.7A X5045V14I-2.7A 2.55-2.7 8-Pin PDIP -40°C–85°C X5043PI-2.7 X5045PI-2.7 8L SOIC 0°C–70°C X5043S8-2.7 X5045S8-2.7 -40°C–85°C X5043S8I-2.7 X5045S8I-2.7 8L MSOP -40°C–85°C X5043M8I-2.7 X5045M8I-2.7 14L TSSOP -40°C–85°C X5043V14I-2.7 X5045V14I-2.7

©Xicor, Inc. 2001 Patents PendingLIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Part Mark Information Blank = 8-Lead SOIC P= 8 Pin Plastic DIP Blank = No suffix, 0°C to +70°C I = No Suffix; –40°C to +85°C A = -4,5A; 0°C to +70°C, IA = -4.5A; –40°C to +85°C FA = -2.7A; 0°C to +70°C GA = -2.7A; –40°C to +85°C X X5043/45 X AEP/AEY = No Suffix; –40°C to +85°C AEN/AEW = -4.5A; –40°C to +85°C AET/AFC = -2.7; –40°C to +85°C AER/AFA = -2.7A; –40°C to +85°C X5043/X5045 YWW XXX PDIP/SOIC MSOP V = 14 Lead TSSOP Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 AM = 5V ±10%, –40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.85-3.0 WX5043/45 X TSSOP