X5043M8Z-45A

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Document overview

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• PDF pages: 21

Technical content

Features

• L o w VCC Detection and Reset Assertion - Four standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption - <50µA max standby current, watchdog on - <10µA max standby current, watchdog off
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock™ Memory - Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection - Write enable latch - Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time - 16-byte page write mode - 5ms write cycle time (typical)
• Available Packages - 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP - 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Communications Equipment - Routers, Hubs, Switches - Set Top Boxes
• Industrial Systems - Process Control - Intelligent Instrumentation
• Computer Systems - Desktop Computers - Network Servers
• Battery Powered Equipment Data Sheet September 23, 2015

2 FN8126.3 September 23, 2015 Typical Application Block Diagram uC RESET CS SCK SI SO WP VCC VSS RESET SPI VCC VSS X5043 2.7-5.0V 10K Watchdog Timer Command Decode & Control Logic SI SO SCK CS/WDI VCC POR and Low Generation VTRIP RESET (X5043) Voltage Reset Protect Logic 4Kbits EEPROM Watchdog Detector WP Array Status Register Transition Reset Reset & Watchdog Timebase RESET (X5045) X5043, X5045 STANDARD VTRIP LEVEL SUFFIX See “Ordering Information” on page 3. for more details For Custom Settings, call Intersil. X5043, X5045

3 FN8126.3 September 23, 2015

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE VTRIP RANGE TEMP RANGE (°C) PACKAGE X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5045P Z AM - 40 to 85 8 Ld PDIP (Pb-free) X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A (Note) X5045 Z AL 0 t o 70 8 Ld SOIC (Pb-free) X5043S8IZ-4.5A* (Note) X5043 Z AM X5045S8IZ-4.5A* (Note) X5045 Z AM -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-4.5A (Note) DBS X5045M8Z-4.5A (Note) (No longer available, recommended replacement: X5045S8Z-4.5A) DCB 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-4.5A (Note) DBM X5045M8IZ-4.5A (Note) (No longer available, recommended replacement: X5045S8IZ-4.5A) DBX -40 to 85 8 Ld MSOP (Pb-free) X5043PZ (Note) X5043P Z X5045PZ (Note) X5045P Z 4.25-4.5 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ (Note) X5043P Z I X5045PIZ (Note) X5045P Z I -40 to 85 8 Ld PDIP (Pb-free) X5043S8Z* (Note) X5043 Z X5045S8Z* (Note) X5045 Z 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ* (Note) X5043 Z I X5045S8IZ* (Note) X5045 Z I -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z (Note) DBN X5045M8Z (Note) (No longer available, recommended replacement: X5045S8Z) DBY 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ (Note) DBJ X5045M8IZ (Note) (No longer available, recommended replacement: X5045S8IZ-2.7) DBT -40 to 85 8 Ld MSOP (Pb-free) X5043V14IZ (Note) (No longer available, recommended replacement: X5043M8IZ) X5043V Z I X5045V14IZ (Note) (No longer available or supported) X5045V Z I -40 to 85 14 Ld TSSOP (Pb-free) X5043, X5045

4 FN8126.3 September 23, 2015 X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP - 40 to 85 8 Ld PDIP (Pb-free) X5043S8Z-2.7A* (Note) X5043 Z AN X5045S8Z-2.7A (Note) X5045 Z AN 0 to 70 8 Ld SOIC (Pb-fr ee) X5043S8IZ-2.7A* (Note) X5043 Z AP X5045S8IZ-2.7A (Note) X5045 Z AP -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-2.7A (Note) DBR X5045M8Z-2.7A (Note) (No longer available, recommended replacement: X5045S8Z-2.7A) DCA 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-2.7A* (Note) DBL X5045M8IZ-2.7A (Note) (No longer available, recommended replacement: X5045S8IZ-2.7A) DBW -40 to 85 8 Ld MSOP (Pb-free) X5043PZ-2.7 (Note) X5043P Z F X5045PZ-2.7 (Note) X5045P Z F 2.55-2. 7 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ-2.7 (Note) X5043P Z G X5045PIZ-2.7 (Note) X5045P Z G -40 t o 85 8 Ld PDIP (Pb-free) X5043S8Z-2.7* (Note) X5043 Z F X5045S8Z-2.7* (Note) X5045 Z F 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ-2.7* (Note) X5043 Z G X5045S8IZ-2.7* (Note) X5045 Z G -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-2.7 (Note) DBP X5045M8Z-2.7 (Note) (No longer available, recommended replacement: X5045S8Z-2.7) DBZ 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-2.7* (Note) DBK X5045M8IZ-2.7 (Note) (No longer available, recommended replacement: X5045S8IZ-2.7) DBU -40 to 85 8 Ld MSOP (Pb-free) *Add "-T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE VTRIP RANGE TEMP RANGE (°C) PACKAGE X5043, X5045

5 FN8126.3 September 23, 2015 Pin Configuration Pin Descriptions Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input. Chip Select (CS/WDI) When CS is high, the X5043, X5045 are deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043, X5045 will be in the standby power mode. CS low enables the X5043, X5045, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043, X5045 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043, X5045. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043, X5045, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer. Principles of Operation Power-on Reset Application of power to the X5043, X5045 activate a Power- on Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V CC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043, X5045 monitor the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With

8 Ld SOIC/PDIP/MSOP

X5043, X5045 VSS SCK SI

14 Ld TSSOP

X5043, X5045 NC NC NC WP NC 5 7VSS NC10 SCK SI Pin Names SYMBOL DESCRIPTION CS/WDI Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage RESET/RESET Reset Output X5043, X5045

remain unchanged, even during total power failure. sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h. VTRIP is reset, the new VTRIP is something less than 1.7V. Note: This operation also writes 00h to array address 03h.

8 Bits

FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.)

FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V) FIGURE 3. SAMPLE VTRIP RESET CIRCUIT

allowing operation on a simple four-wire bus. minimum data retention of 100 years. popular microcontroller families. where left off. CS must be LOW during the entire operation. Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. FIGURE 4. VTRIP PROGRAMMING SEQUENCE TABLE 1. INSTRUCTION SET

necessary to send a byte address or data. the watchdog timer and the memory block lock protection. WRDS instruction resets the WEL bit. disable block lock protection of that portion of memory. programmed with the WRSR instruction. the WREN instruction into the device and pull CS HIGH. and WRSR, the WRSR instruction is ignored.

00 W D 1 W D 0 B L 1 B L 0 W E L W I P

FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE

the next higher address after each byte of data is shifted out. the WREN instruction into the device and pull CS HIGH. followed by the 8-bit address and then the data to be written. that has been previously written. FIGURE 8. READ EEPROM ARRAY SEQUENCE

1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an

active state and receive an instruction.

1. SO pin is high impedance.
2. The Write Enable Latch is reset.
3. Reset Signal is active for t

• A WREN instruction must be issued to set the Write Enable Latch.
• C S must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
• Block Protect bits provide additional level of write protection for the memory array.
• T h e W P pin LOW blocks nonvolatile write operations. 24 25 26 27 28 29 30 31 SCK SI CS 0123456789 1 0 SCK SI Instruction 8 Bit Address Data Byte 1 76543210 CS 32 33 34 35 36 37 38 39 Data Byte 2 76543210 Data Byte 3 76543210 Data Byte N 765 3210 12 13 14 15 16 17 18 19 20 21 22 23 654 3210 9th Bit of Address

FIGURE 9. WRITE MEMORY SEQUENCE

13 FN8126.3 September 23, 2015 NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 3. SCK frequency measured from V CC x 0.1/VCC x 0.9 Absolute Maximum Ratings Reco mmended Operating Conditions Voltage on any pin with respect to V Temperature: Supply Voltage: CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SYMBOL PARAMETER TEST CONDITIONS/COMMENTS LIMITS UNITMIN TYP (2) MAX ICC1 VCC Write Current (Active) SCK = 3.3MHz (3); SO, RESET, RESET = Open 3 mA ICC2 VCC Read Current (Active) SCK = 3.3MHz (3); SI = VSS, RESET, RESET = Open 2m A ISB1 VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC =5 . 5 V 1 0 µ A ISB2 VCC Standby Current WDT = ON CS = VCC, SCK, SI = VSS, VCC =5 . 5 V 5 0 µ A ILI Input Leakage Current SCK, SI, WP = V SS to VCC 0 . 1 1 0 µ A ILO Output Leakage Current SO, RESET , RESET = VSS to VCC 0.1 10 µA VIL(1) Input LOW Voltage SCK, SI, WP , CS -0.5 V CC x 0.3 V VIH(1) Input HIGH Voltage SCK, SI, WP , CS VCC x 0.7 V CC + 0.5 V VOL Output LOW Voltage (SO) I OL = 2mA @ VCC = 2.7V IOL = 0.5mA @ VCC = 1.8V 0.4 V VOH1 Output HIGH Voltage (SO) V CC > 3.3V, IOH = –1.0mA V CC - 0.8 V VOH2 Output HIGH Voltage (SO) 2V < V CC  3.3V, IOH = –0.4mA V CC - 0.4 V VOH3 Output HIGH Voltage (SO) V CC  2V, IOH = –0.25mA V CC - 0.2 V VOLRS Output LOW Voltage (RESET, RESET) IOL = 1mA 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST CONDITIONS MAX UNIT COUT(2) Output Capacitance (SO, RESET, RESET) V OUT = 0V 8 pF CIN(2) Input Capacitance (SCK, SI, CS, WP)V IN = 0V 6 pF X5043, X5045

14 FN8126.3 September 23, 2015 Equivalent A.C. Load Circuit at 5V VCC NOTES: 4. This parameter is periodically sampled and not 100% tested. 5. t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Output 30pF 4.6k RESET/RESET 30pF 1.64k 1.64k A.C. Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 SYMBOL PARAMETER 2.7V–5.5V UNITMIN MAX DATA INPUT TIMING fSCK Clock Frequency 0 3.3 MHz tCYC Cycle Time 300 ns tLEAD CS Lead Time 150 ns tLAG CS Lag Time 150 ns tWH Clock HIGH Time 130 ns tWL Clock LOW Time 130 ns tSU Data Setup Time 30 ns tH Data Hold Time 30 ns tRI(4) Input Rise Time 2µ s tFI(4) Input Fall Time 2µ s tCS CS Deselect Time 100 ns tWC(5) Write Cycle Time 10 ms Data Output Timing SYMBOL PARAMETER 2.7–5.5V UNIT MIN MAX fSCK Clock Frequency 0 3.3 MHz tDIS Output Disable Time 150 ns tV Output Valid from Clock Low 120 ns tHO Output Hold Time 0 ns tRO(4) Output Rise Time 50 ns tFO(4) Output Fall Time 50 ns X5043, X5045

15 FN8126.3 September 23, 2015 Serial Output Timing Serial Input Timing Symbol Table SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB In tSU tRI tLAGtLEAD tH LSB In tCS tFI High Impedance WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X5043, X5045

16 FN8126.3 September 23, 2015 Power-Up and Power-Down Timing NOTE: 6. This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing VCC tPURST tF tRPD RESET (X5043)

0 Volts

RESET (X5045) VTRIP tPURST tR RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT VTRIP Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V t PURST Power-up Reset Time Out 100 200 400 ms tRPD(6) VCC Detect to Reset/Output 500 ns tF(6) VCC Fall Time 10 µs tR(6) VCC Rise Time 0.1 ns VRVALID Reset Valid VCC 1V CS/WDI tCST RESET RESET tWDO tRSTtWDO tRST (5043) (5045) RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 1 (default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 200 600 1.4 300 800 ms ms sec tCST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time Out 100 200 400 ms X5043, X5045

17 FN8126.3 September 23, 2015 VTRIP Programming Timing Diagram SCK SI CS 01h or VCC (VTRIP) WP tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 02h 06h 03h VTRIP Programming Parameters PARAMETER DESCRIPTION MIN MAX UNIT tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tPCS VTRIP Programming CS inactive time 1 µs tTSU VTRIP Setup time 1µ s tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 1.7 4.75 V Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. X5043, X5045

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8126.3 September 23, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 23, 2015 FN8126.3 - Updated Ordering Information Table on page 3. - Added Revision History. - Added About Intersil Verbiage. - Attached current POD. X5043, X5045

19 FN8126.3 September 23, 2015 Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c X5043, X5045

20 FN8126.3 September 23, 2015 Package Outline Drawing M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12 DETAIL "A" TOP VIEW INDEX AREA 12 3 -C- SEATING PLANE x 45° NOTES: 6. Dimensioning and tolerancing per ANSI Y14.5M-1994. 7. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 8. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 9. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 10. Terminal numbers are shown for reference only. 11. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 12. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13. This outline conforms to JEDEC publication MS-012-AA ISSUE C. SIDE VIEW “A SIDE VIEW “B” 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 4 5 TYPICAL RECOMMENDED LAND PATTERN 2.20 (0.087) 0.60 (0.023) X5043, X5045

21 FN8126.3 September 23, 2015 Package Outline Drawing M8.118

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 7/11 DETAIL "X" SIDE VIEW 2 TYPICAL RECOMMENDED LAND PATTERN TOP VIEW PIN# 1 ID 0.25 - 0.36 DETAIL "X" 0.10 ± 0.05 (4.40) (3.00) (5.80) H C

1.10 MAX

0.09 - 0.20 3°±3° GAUGE PLANE 0.25

0.95 REF

0.55 ± 0.15 B

0.08 C A-B D

3.0±0.05 0.85±010 SEATING PLANE A

0.65 BSC

3.0±0.05 4.9±0.15 (0.40) (1.40) (0.65) D SIDE VIEW 1 Dimensioning and tolerancing conform to JEDEC MO-187-AA Plastic interlead protrusions of 0.15mm max per side are not Dimensions in ( ) are for reference only. Dimensions are measured at Datum Plane "H". Plastic or metal protrusions of 0.15mm max per side are not Dimensions are in millimeters. NOTES: and AMSEY14.5m-1994. included. included. 0.10 CM X5043, X5045