X5001S8-2.7

X5001 INTERSIL | Alldatasheet

Document overview

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Technical content

FN8125.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X5001 CPU Supervisor

FEATURES

• 200ms power-on reset delay
• L o w VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
• Selectable nonvolatile watchdog timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software
• Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off
• 2.7V to 5.5V operation
• SPI mode 0 interface
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Watchdog change latch
• High reliability
• Available packages —8-lead TSSOP —8-lead SOIC —8 pin PDIP

DESCRIPTION

This device combines three popular functions, Power- on Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The watchdog timer provides an independent protec- tion mechanism for microc ontrollers. During a system failure, the device w ill respond with a RESET signal after a selectable time out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage condi- tions by the device’s low V CC detection circuitry. When VCC falls below the minimum VCC trip point, the system is reset. RESET is asserted until VCC returns to proper operating levels and stabilizes. Five industry standard V TRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. The device utilizes Intersil’s proprietary Direct Write cell for the watchdog timer control bits and the V TRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. BLOCK DIAGRAM Watchdog Timer Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Watchdog Transition Detector Reset & Watchdog Timebase Power-on/ Generation VTRIP RESET REset Low Voltage Data Sheet April 6, 2005

2 FN8125.0 April 6, 2005 PIN CONFIGURATION PIN DESCRIPTION Pin (SOIC/PDIP) Pin TSSOP Name Function 11 C S /WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch- dog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET /RESET going active. 22 S O Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 58 S I Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 69 S C K Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 36 V PE VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V).

47 V SS Ground

7 13 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active un- til VCC rises above the minimum VCC sense level for 200ms. RESET goes active if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long- er than the selectable watchdog time out period. A falling edge of CS/WDI will reset the watchdog timer. RESET goes active on power-up at 1V and remains active for 200ms after the power supply stabilizes. 3-5,10-12 NC No internal connections 8-Lead SOIC/PDIP X5001 CS/WDI SO RESET VCC VSS SCK SI SCK SI VSS VCC CS/WDI SO 8-Lead TSSOP RESET VPE VPE X5001 X5001

3 FN8125.0 April 6, 2005 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5001 activates a power- on reset circuit. This circuit goes active at 1V and pulls the RESET /RESET pin active. Th is signal prevents the system micropro cessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V CC exceeds the device V TRIP value for 200ms (nominal) the circuit releases RESET , allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5001 monitors the V CC level and asserts RESET if supply voltage falls below a pre- set minimum V TRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds V TRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microproces- sor must toggle the CS /WDI pin periodically to prevent a RESET signal. The CS /WDI pin must be toggled from HIGH to LOW prior to the expiration of the watch- dog time out period. The state of two nonvolatile control bits in the watchdog register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard V CC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applica- tions where the standard V TRIP is not exactly right, or if higher precision is needed in the V TRIP value, the X5001 threshold may be adjusted. The procedure is described below, and requires the application of a high voltage control signal. Setting the V TRIP Voltage This procedure is used to set the V TRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new V TRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new V TRIP voltage, apply the desired V TRIP threshold voltage to the VCC pin and tie the WPE pin to the programming voltage VP. Then a VTRIP programming command sequence is sent to the device over the SPI interface. This V TRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the V TRIP programming sequence. VP is brought LOW to end the operation. Resetting the VTRIP Voltage This procedure is used to set the V TRIP to a “native” voltage level. For example, if the current V TRIP is 4.4V and the new VTRIP must be 4.0V, then the V TRIP must be reset. When VTRIP is reset, the new VTRIP is some- thing less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the V TRIP voltage, apply greater than 3V to the VCC pin and tie the W PE pin to the programming voltage VP. Then a V TRIP command sequence is sent to the device over the SPI interface. This V TRIP pro- gramming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the V TRIP programming sequence. V P is brought LOW to end the operation. X5001

Figure 1. Sample VTRIP Reset Circuit Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP value) Figure 3. Reset VTRIP Level Sequence (VCC > 3V)

16 Bits

Figure 4. VTRIP Programming Sequence popular microcontroller families. it again to resume operations where left off.

settings and data bits 0, 1, 2, 5, 6 and 7 must be “0”. after the completion of a valid nonvolatile write cycle. reserved and will return’0’ when read. See Figure 3. the current status of the watchdog control bits. requires a pull up resistor. – The device is in the low power standby state. an active state and receive an instruction. – The watchdog change latch is reset. signal is active for tPURST. change to the watchdog timeout setting. Table 1. Instruction Set Definition Note: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.

000 W D 1 WD0 00 0

9 FN8125.0 April 6, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specifi- cation) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Unit Test ConditionsMin. Typ Max. ICC1 VCC write current (Active) 5m A S C K = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ICC2 VCC read current (Active) 0.4 mA SCK = V CC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ISB1 VCC standby current WDT=OFF 1µ A C S = VCC, VIN = VSS or VCC, VCC = 5.5V ISB2 VCC standby current WDT=ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC standby current WDT=ON 20 µA CS = V CC, VIN = VSS or VCC, VCC = 3.6V ILI Input leakage current 0.1 10 µA V IN = VSS to VCC ILO Output leakage current 0.1 10 µA V OUT = VSS to VCC VIL(1) Input LOW voltage -0.5 V CC x 0.3 V VIH(1) Input HIGH voltage V CC x 0.7 V CC + 0.5 V VOL1 Output LOW voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < V CC < 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V V CC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH voltage V CC-0.8 V V CC > 3.3V, IOH = -1.0mA VOH2 Output HIGH voltage V CC-0.4 V 2V < V CC ≤ 3.3V, IOH = -0.4mA VOH3 Output HIGH voltage V CC-0.2 V V CC ≤ 2V, IOH = -0.25mA VOLRS Reset output LOW voltage

0.4 V I OL = 1mA

RECOMMENDED OPERATING CONDITIONS Note: PT= Package, Temperature Temperature Min. Max. Commercial 0°C +70°C Voltage Option Supply Voltage Limits -1.8 1.8V to 3.6V -2.7 or -2.7A 2.7V to 5.5V -4.5 or -4.5A 4.5V to 5.5V X5001

10 FN8125.0 April 6, 2005 POWER-UP TIMING CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Notes: (1) V IL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter Min. Max. Unit tPUR(2) Power-up to read operation 1 ms tPUW(2) Power-up to write operation 5 ms Symbol Test Max. Unit Conditions COUT(2) Output capacitance (SO, RESET)8 p F V OUT = 0V CIN(2) Input capacitance (SCK, SI, CS)6 p F V IN = 0V Output 100pF 3.3kΩ RESET 30pF 1.64kΩ 1.64kΩ Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x0.5 SymboL Parameter UnitMin. Max. Min. Max. fSCK Clock frequency 0 1 0 2 MHz tCYC Cycle time 1000 500 ns tLEAD CS lead time 400 200 ns tLAG CS lag time 400 200 ns tWH Clock HIGH time 400 200 ns tWL Clock LOW time 400 200 ns tSU Data setup time 100 50 ns tH Data hold time 100 50 ns tRI(3) Input rise time 2 2 µs tFI(3) Input fall time 2 2 µs tCS CS deselect time 250 150 ns tWC(4) Write cycle time 10 10 ms X5001

Figure 12. Power-Up and Power-Down Timing Note: (5) This parameter is periodically sampled and not 100% tested.

0 Volts

Figure 13. CS vs. RESET Timing

14 FN8125.0 April 6, 2005 VTRIP Programming Parameters Parameter Description Min. Max. Unit tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1 µs tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tVPO VTRIP program enable voltage Off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25°C.] -25 +25 mV Vtr VTRIP program voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. X5001

15 FN8125.0 April 6, 2005 Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 3V) Watchdog Timer Off (VCC = 3V, 5V) -40C 25C 90C Temp (c) Isb (µA) VCC Supply Current vs. Temperature (ISB)t WDO vs. Voltage/Temperature (WD1, 0 = 1, 1) VTRIP vs. Temperature (programmed at 25°C) t WDO vs. Voltage/Temperature (WD1, 0 = 1, 0) tPURST vs. Temperature t WDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.7 3.1 4.5 90°C 25°C -40°C Reset (seconds) Voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 8 5 Voltage Temperature VTRIP = 5V VTRIP = 3.5V VTRIP = 2.5V 0.85 0.80 0.75 0.70 0.65 0.60 1.7 4.5 Reset (seconds) Voltage 3.1 90°C 25°C -40°C 275 270 265 260 255 250 245 240 235 -40 25 90 Degrees °C 280Time (ms) 90°C 25°C -40°C 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.29 Reset (seconds) Voltage 1.7 3.1 4.5 0.35 0.55 1.0 0.30 X5001

16 FN8125.0 April 6, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

17 FN8125.0 April 6, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical X5001

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8125.0 April 6, 2005

Ordering Information

VCC Range V TRIP Range Package Operating Temperature Range Part Number RESET (Active LOW) 8-Lead SOIC 0-70°C X5001S8-4.5A 8-Lead TSSOP 0-70°C X5001V8-4.5A 8-Lead SOIC 0-70°C X5001S8 8-Lead TSSOP 0-70°C X5001V8 8-Lead TSSOP 0-70°C X5001V8-2.7 8-Lead TSSOP 501AG = 1.8 to 3.6V, 0 to +70°C, VTRIP = 1.7-1.8V YWW XXXXX 501AH = 1.8 to 3.6V, -40 to +85°C, VTRIP = 1.7-1.8V 501F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V 501G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V X501 = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V 501I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V 8-Lead SOIC X5001 YWW XX AG = 1.8 to 3.6V, 0 to +70°C, VTRIP = 1.7-1.8V AH = 1.8 to 3.6V, -40 to +85°C, VTRIP = 1.7-1.8V F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.55-2.7V G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.55-2.7V I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.25-4.5V 501AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V 501AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V 501AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V 501AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85-3.0V AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85-3.0V AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.5-4.75V AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.5-4.75V Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.25-4.5V YWW = year/work week device is packaged. X5001