X5001P-4.5A

X5001 XICOR | Alldatasheet

Document overview

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Technical content

Features

• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion —Five Standard Reset Threshold Voltages —Adjust Low Vcc Reset Threshold Voltage using special programming sequence —Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile Watchdog Timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software
• Long Battery Life With Low Power Consumption —<50 m A Max Standby Current, Watchdog On —<1 m A Max Standby Current, Watchdog Off
• 2.7V to 5.5V Operation
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Watchdog Change Latch
• High Reliability
• Available Packages —8-Lead TSSOP —8-Lead SOIC —8 Pin PDIP

DESCRIPTION

This device combines three popular functions, Power on Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reli- ability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage condi- tions by the device’s low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET is asserted until Vcc returns to proper operating levels and stabilizes. Five industry standard V TRIP thresholds are available, however, Xicor’s unique circuits allow the thresold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The device utilizes Xicor’s proprietary Direct Write TM cell for the Watchdog TImer control bits and the V TRIP stor- age element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. Block Diagram DATA REGISTER COMMAND DECODE & CONTROL LOGIC SI SO SCK CS /WDI

7036 FRM 01

V CC WATCHDOG TRANSITION DETECTOR RESET & WATCHDOG TIMEBASE POWER ON/ GENERATION V TRIP RESET RESET LOW VOLTAGE

Figure 1. PIN CONFIGURATION

11 C S /WDI

22 S O

out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

58 S I

input data. Send all opcodes (Table 1), addresses and data MSB first. be pulled to a high voltage (15-18V). mains active for 200ms after the power supply stabilizes.

8 Lead SOIC/PDIP

8 Lead TSSOP

Application of power to the X5001 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET /RESET pin active. This signal prevents the sys- tem microprocessor from starting to operate with insuffi- cient voltage or prior to stabilization of the oscillator. When Vcc exceeds the device V TRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Low voltage monitoring During operation, the X5001 monitors the V CC level and asserts RESET if supply voltage falls below a preset mini- mum V TRIP . The RESET signal prevents the microproces- sor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds V TRIP for 200ms. watchdog timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS /WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time- out period. The state of two nonvolatile control bits in the Watchdog Register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard Vcc threshold TRIP ) voltage. This value will not change over normal operating and storage conditions. However, in applica- tions where the standard V TRIP is not exactly right, or if higher precision is needed in the V TRIP value, the X5001 threshold may be adjusted. The procedure is described below, and requires the application of a high voltage con- trol signal. Setting the V TRIP Voltage This procedure is used to set the V TRIP to a higher volt- age value. For example, if the current V TRIP is 4.4V and the new V TRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the cur- rent setting, then it is necessary to reset the trip point before setting the new value. To set the new V TRIP voltage, apply the desired V TRIP threshold voltage to the Vcc pin and tie the W PE pin to the programming voltage V P . Then a V TRIP programming command sequence is sent to the device over the SPI interface. This V TRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the V TRIP programming sequence. V P is brought LOW to end the operation. Resetting the V TRIP Voltage This procedure is used to set the V TRIP to a “native” volt- age level. For example, if the current V TRIP is 4.4V and the new V TRIP must be 4.0V, then the V TRIP must be reset. When V TRIP is reset, the new V TRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the V TRIP voltage, apply greater than 3V to the Vcc pin and tie the W PE pin to the programming voltage Vp. Then a V TRIP command sequence is sent to the device over the SPI interface. This V TRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the V TRIP programming sequence. V P is brought LOW to end the operation.

Figure 2. Sample V Figure 3. Set V Figure 4. Reset V

16 BITS

Figure 5. Vtrip Programming Sequence

The device is designed to interface directly with the syn- chronous Serial Peripheral Interface (SPI) of many popu- lar microcontroller families. The device monitors the CS /WDI line and asserts RESET output if there is no activity within user selctable time-out period. The device also monitors the Vcc supply and asserts the RESET if Vcc falls below a preset minimum TRIP ). The device contains an 8-bit Watchdog Timer Register to control the watchdog time-out period. The cur- rent settings are accessed via the SI and SO pins. All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Watchdog Timer Register Watchdog Timer Control Bits The Watchdog Timer Control bits, WD and WD , select the Watchdog Time-out Period. These nonvolatile bits are programmed with the Set Watchdog Timer (SWDT) instruction. Write Watchdog Register Operation Changing the Watchdog Timer Register is a two step pro- cess. First, the change must be enabled with by setting the Watchdog Change Latch (see below). This instruction is followed by the Set Watchdog Timer (SWDT) instruc- tion, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the Watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be “0” . Watchdog Change Latch The Watchdog Change Latch must be SET before a Write Watchdog Timer Operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (See Figure 2.) This latch is automati- cally reset upon a power-up condition and after the com- pletion of a valid nonvolatile write cycle. Read Watchdog Timer Register Operation If there is not a nonvolatile write in progress, the Read Watchdog Timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return ’0’ when read. See Figure 3. If a nonvolatile write is in progress, the Read Watchdog Timer Register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a seperate Read Watchdog Timer instruction should be used to determine the current status of the Watchdog control bits. RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the Watchdog timer has reached its programmable time-out limit. The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state:

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The Watchdog Change Latch is reset.
• The RESET Signal is active for tPURST . Data Protection The following circuitry has been included to prevent inad- vertent writes:
• A EWDC instruction must be issued to enable a change to the watchdog timeout setting.
• C S must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting. 7 6543210 00 0 WD 1 WD 0 000 Watchdog Control Bits Watchdog Time-out (Typical)WD1 WD0 0 0 1.4 Seconds 0 1 600 Milliseconds 1 0 200 Milliseconds 1 1 Disabled

Table 1. Instruction Set Definition Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.

7038 FRM T03

Figure 1. Read Watchdog Timer setting Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence See Watchdog Timer Settings and Figure 3.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) POWER-UP TIMING CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Units Test ConditionsMin. Typ. Max. ICC1 VCC Write Current (Active) 5m A SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ICC2 VCC Read Current (Active) 0.4 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ISB1 VCC Standby Current WDT=OFF 1 µA CS = VCC , VIN = VSS or VCC , VCC = 5.5V ISB2 VCC Standby Current WDT=ON 50 µA CS = VCC , VIN = VSS or VCC , VCC = 5.5V ISB3 VCC Standby Current WDT=ON 20 µA CS = VCC , VIN = VSS or VCC , VCC =3.6V ILI Input Leakage Current 0.1 10 µA V IN = VSS to VCC ILO Output Leakage Current 0.1 10 µA V OUT = VSS to VCC VIL (1) Input LOW Voltage –0.5 V CC x0.3 V VIH (1) Input HIGH Voltage V CC x0.7 V CC +0.5 V VOL1 Output LOW Voltage 0.4 V V CC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < V CC < 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC £ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage V CC –0.8 V V CC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage V CC –0.4 V 2V < VCC £ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage V CC –0.2 V VCC £ 2V, IOH = –0.25mA VOLRS Reset Output LOW Voltage 0.4 V I OL = 1mA Symbol Parameter Min. Max. Units tPUR (2) Power-up to Read Operation 1m s tPUW (2) Power-up to Write Operation 5m s Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO, RESET) 8p F V OUT = 0V C IN (2) Input Capacitance (SCK, SI, CS) 6p F V IN = 0V ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Respect to V RECOMMENDED OPERATING CONDITIONS

7036 FRM T07

*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PT= Package, Temperature Temp Min. Max. Commercial 0°C +70°C Voltage Option Supply Voltage Limits –1.8 1.8V to 3.6V –2.7 or -2.7A 2.7V to 5.5V –4.5 or -4.5A 4.5V to 5.5V

Notes: (3) This parameter is periodically sampled and not 100% tested.

Figure 1. Power-Up and Power-Down Timing Notes: (5) This parameter is periodically sampled and not 100% tested. Figure 2. CS vs. RESET Timing

0 Volts

VTRIP Programming Timing Diagram SCK SI CS 0001h or 02h Vcc (VTRIP) VPE tTSU tTHD tVPHtVPS VP VTRIP tRP tVPOtPCS 0003h0001h 03h

VTRIP Programming Parameters Parameter Description Min Max Units tVPS VTRIP Program Enable Voltage Setup time 1 ms tVPH VTRIP Program Enable Voltage Hold time 1 ms tPCS VTRIP Programming CS inactive time 1 ms tTSU VTRIP Setup time 1 ms tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0u s tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (Vcc applied - VTRIP) (Programmed at 25oC.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(Vcc applied - Vta1) - VTRIP. Programmed at 25oC.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25oC.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75oC). (Programmed at 25oC.) -25 +25 mV VTRIP Programming parameters are periodically sampled and are not 100% Tested.

Watchdog Timer On (Vcc = 5V) Watchdog Timer On (Vcc = 3V) Watchdog Timer Off (Vcc = 3V, 5V) –40C 25C 90C Temp (c) Isb (uA) Vcc Supply Current vs. Temperature (ISB )t WDO vs. Voltage/Temperature (WD1,0=1,1) VTRIP vs. Temperature (programmed at 25°C) t WDO vs. Voltage/Temperature (WD1,0=1,0) tPURST vs. Temperature t WDO vs. Voltage/Temperature (WD1,0 0=0,1) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.7 3.1 4.5 90°C 25°C –40°C Reset (seconds) Voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 02 5 8 5 Voltage Temperature Vtrip=5V Vtrip=3.5V Vtrip=2.5V 0.85 0.80 0.75 0.70 0.65 0.60 1.7 4.5 Reset (seconds) Voltage 3.1 90°C 25°C –40°C 275 270 265 260 255 250 245 240 235 –40 25 90 Degrees °C 280Time (ms) 90°C 25°C –40°C 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.29 Reset (seconds) Voltage 1.7 3.1 4.5 0.35 0.55 1.0 0.30

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7¥ 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0¥ – 8¥ X 45¥ 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0¥ – 8¥ .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Ordering Information

Vcc Range Vtrip Range Package Operating Temperature Range PART NUMBER RESET (Active LOW) 8 pin PDIP 0oC - 70oC X5001P-4.5A 8L SOIC 0oC - 70oC X5001S8-4.5A 8L TSSOP 0oC - 70oC X5001V8-4.5A 8 pin PDIP 0oC - 70oC X5001P 8L SOIC 0oC - 70oC X5001S8 8L TSSOP 0oC - 70oC X5001V8 2.7-5.5V 2.55-2.7 8L SOIC 0oC - 70oC X5001S8-2.7 8L TSSOP 0oC - 70oC X5001V8-2.7

501AG = 1.8 to 3.6V, 0 to +70°C, VTRIP=1.7-1.8V YWW XXXXX 501AH = 1.8 to 3.6V, -40 to +85°C, VTRIP=1.7-1.8V 501F = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.55-2.7V 501G = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.55-2.7V 501 = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.25-4.5V 501I = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.25-4.5V 8-Lead SOIC X5001 YWW XX AG = 1.8 to 3.6V, 0 to +70°C, VTRIP=1.7-1.8V AH = 1.8 to 3.6V, -40 to +85°C, VTRIP=1.7-1.8V F = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.55-2.7V G = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.55-2.7V I = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.25-4.5V 501AN = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.85-3.0V 501AP = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.85-3.0V 501AL = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.5-4.75V 501AM = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.5-4.75V AN = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.85-3.0V AP = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.85-3.0V AL = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.5-4.75V AM = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.5-4.75V Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.25-4.5V YWW = year/work week device is packaged. LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appro- priate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.