X4C105 INTERSIL | Alldatasheet

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FN8124.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X4C105 4K, NOVRAM/EEPROM CPU Supervisor with NOVRAM and Output Ports

FEATURES

  • 4Kbit serial EEPROM —400kHz serial interface speed —16-byte page write mode
  • One nibble NOVRAM —120ns NOVRAM access speed —AUTOSTORE —Direct/bus access of NOVRAM bits
  • Four output ports
  • Operates at 3.3V ± 10%
  • Low voltage reset when V CC < 3V —3% accurate thresholds available —Output signal shows low voltage condition —Activates NOVRAM AUTOSTORE —Internal block on EEPROM operation
  • Max EEPROM/NOVRAM nonvolatile write cycle: 5ms
  • High reliability —1,000,000 endurance cycles —Guaranteed data retention: 100 years
  • 20-lead TSSOP package

DESCRIPTION

The low voltage X4C105 co mbines several functions into one device. The first is a 2-wire, 4Kbit serial EEPROM memory with write protection. A Write Pro- tect (WP) pin provides har dware protection for the upper half of this memory against inadvertent writes. A one nibble NOVRAM is provided and occupies a sin- gle location. This allows ac cess of 4-bits in a single 150ns cycle. This is useful for tracking system opera- tion or process status. The NOVRAM memory is com- pletely isolated from the serial memory section. A low voltage detect ci rcuit activates a RESET pin when V CC drops below 3V. This signal also blocks new read or write operations and initiates a NOVRAM AUTOSTORE. The AUTOSTORE operation is pow- ered by an external capacitor to ensure that the value in the NOVRAM is always maintained in the event of a power failure. The four NOVRAM bits also appear on four separate output pins to allow continuous control of external cir- cuitry, such as ASICs. Intersil EEPROMs are designed and tested for appli- cations requiring extended endurance. Inherent data retention is greater than 100 years. BLOCK DIAGRAM Command Decodeand Control Logic HV Generation Timing and Control EEPROMArray X Decoder Y Decoder Data Register Write Control LogicWP SCL SDA CE OE WE I/O Buffers Control Logic and Timing Static RAM Memory EEPROM Memory VCC VSS RESET Voltage MonitorPower-on Reset Low Voltage Detect CAP Supply Output Buffers and Latches 4Kbits Data Sheet March 18, 2005

2 FN8124.0 March 18, 2005 PACKAGE/PINOUTS Pin Names DEVICE DESCRIPTION Serial Memory Section The device contains a 4Kbit EEPROM memory array with an internal address counter that allows it to be read sequentially, through its entire address space after receiving only 1 full address. The serial interface includes a current address read that requires no input address, but allows reading of the entire array starting from the address plus one of the last read or write. The address counter is also used for the write operation where the user may enter up to a page of data (16 bytes) after supplying only 1 full address. A WP pin provides hardware write protection. The WP pin active (HIGH) prevents writes to the top half of the memory. This section is a 4K-bit version of an industry standard 24C04 device. NOVRAM Section The X4C105 also contains a single nibble of NOVRAM, with parallel access. This memory is com- pletely isolated from the serial memory section. The NOVRAM is intended to connect to the system mem- ory bus and uses standard CE , OE, and WE pins to control access. A NOVRAM (or nonvolatile RAM) consists of an SRAM part and an EEPROM part. The SRAM is saved to EEPROM only when po wer fails and the EEPROM is recalled to SRAM only on power-up. Output Ports The X4C105 has four output only ports. These are active whenever power is applied to the device. The state of the output pin reflects the value in the respec- tive SRAM bit. As such, these port pins provide a non- volatile state. The conditions on the pins are restored when power is re-applied to the device. This can be valuable as a DIP switch replacement for controlling the conditions of an ASIC or other system logic. Low Voltage Detection When the internal low voltage detect circuitry senses that V CC is low, several things happen: – The RESET pin goes active. – The contents of the SRAM are automatically saved to the “shadow” EEPROM. – Internal circuitry switches to provide power for the AUTOSTORE operation from the CAP pin so the store operation can complete even in the event of a catastrophic power failure. To insure this, it is rec- ommended that a 47µF capacitor be used on the CAP pin. The capacitor is continuously charged dur- ing normal operation to provide the necessary charge to complete the store operation. Other inter- nal circuits are turned off to minimize current con- sumption during the store operations. — Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the operation is com- pleted and is followed by a NOVRAM AUTOSTORE cycle. Pin Description VSS Ground SDA Serial Data VCC Power SCL Serial Clock WP Write Protect S1, S2 Device Select Inputs CAP External AUTOSTORE Capacitor D0-D3 NOVRAM I/Os RESET Low Voltage Detect Output CE NOVRAM Chip Enable OE NOVRAM Read Signal WE NOVRAM Write signal O0-O3 NOVRAM Outputs VCC SDA SCL CAP WP RESET CE WE OE VSS 20-Lead TSSOP X4C105

put is at high impedance. See Figure 5. over-writes the previous data, one byte at a time. Figure 5. Byte Write Sequence Figure 6. Writing 12 bytes to a 16-byte page starting at location 10.

5 Bytes

7 Bytes

acknowledge, and data transfer sequence. contents of the array will not be affected. Figure 7. Page Write Operation

device initiates the internal non volatile write cycle. host can then proceed with the read or write operation. Refer to the flow chart in Figure 8. Figure 8. Acknowledge Polling Sequence operation for initialization. the address, acknowledge, and data transfer sequence. the ninth clock cycle and then issue a stop condition. master must first perform a “dummy” write operation. acknowledge, and data transfer sequence.

Figure 11. Sequential Read Sequence is undefined on a power-up condition. tects the upper half of the array. Table 1. Write Protected Areas

10 FN8124.0 March 18, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specifi- cation) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS V CC = 3.0 to 3.6V at -40°C to +85°C unless otherwise specified. Notes: (1) The device enters the active state after any start, and re mains active until: 9 clock cyc les later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, exce pt those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) V IL min. and VIH max. are for reference only and are not tested. Symbol Parameter Min. Max. Unit Test Conditions ICC1(1) Active supply current serial read or serial write (does not include the nonvolatile store operation) 2.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, SDA = Read/Write Operation, CE, OE, WE, D0-D3 = VIH; O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC2(1) Average active supply current during serial non- volatile store operation 3.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, CE, OE, WE, D0-D3 = VIH; O0-O3, RESET = Open CAP is tied to VCC. Test during the N.V. write cycle. ICC3(1) Active supply current volatile NOVRAM read 3.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, WE = VIH; CE, OE = VIL, D0-D3, O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC4(1) Active supply current volatile NOVRAM write 3.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 =VIL, OE = VIH; CE, WE = VIL, D0-D3 = VIL or VIH, O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP ICC5(1) Average active supply current over NOVRAM store, or active current dur- ing recall 3.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, VIH; WP, S1, S2 = VIL, WE, CE, OE = VIH; D0-D3, O0-O3, RESET = Open CAP is tied to VCC, VCC < VTRIP for Store; VCC > VTRIP for Re- call ISB1(1) Standby current 50 µAV IL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, CE, WE, OE, D0-D3, = VIH, WP = VIL, O0-O3, RESET = Open; CAP is tied to VCC ILI Input leakage current 10 µAV IN = GND to VCC ILO Output leakage current 10 µAV SDA = GND to VCC; Device is in Standby(2) VIL(3) Input LOW voltage -0.5 V CC x 0.3 V VIH(3 Input HIGH voltage V CC x 0.7 V CC + 0.5 V VHYS Schmitt trigger input hysteresis .05 x VCC V VOL Output LOW voltage 0.4 V I OL = 2.0mA, VCC = 3.3V VOH Output HIGH voltage V CC - 0.4 V I OH = -1mA, VCC = 3.3V X4C105

11 FN8124.0 March 18, 2005 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 3.0-3.6V Note: (4) This parameter is periodically sampled and not 100% tested. SERIAL NONVOLATILE WRITE CYCLE TIMING Note: (5) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. SERIAL MEMORY AC CHARACTERISTICS Serial AC Test Conditions Equivalent AC Output Load Circuit for VCC = 3.0-3.6V Symbol Parameter Max. Unit Test Conditions CI/O(4) Input/output capacitance (SDA, D0-D3, O0-O3) 8 pF V I/O = 0V CIN(4) Input capacitance (SCL, WP, CE, WE, OE, S1, S2) 6 pF V IN = 0V Symbol Parameter Min. Typ. (5) Max. Unit tWC(5) Write cycle time 3 5 ms Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load SDA 1533Ω 100pF 3.3V For VOL = 0.4V and IOL = 2mA X4C105

12 FN8124.0 March 18, 2005 SERIAL AC SPECIFICATIONS TA = -40°C to +85°C, VCC = +3.0V to +3.6V, unless otherwise specified. Notes: (7) This parameter is periodically sampled and not 100% tested. (8) Cb = total capacitance of one bus line in pF. SERIAL TIMING DIAGRAMS Bus Timing Symbol Parameter 400kHz Option UnitMin. Max. fSCL SCL clock frequency 0 400 kHz tIN Pulse width of spikes to be suppressed by the input filter 0 50 ns tAA SCL LOW to SDA data out valid 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW time 1.3 µs tHIGH Clock HIGH time 0.6 µs tSU:STA Start condition setup time 0.6 µs tHD:STA Start condition hold time 0.6 µs tSU:DAT Data in setup time 100 ns tHD:DAT Data in hold time 0 µs tSU:STO Stop condition setup time 0.6 µs tDH Data output hold time 50 ns tR SDA and SCL rise time 20 +.1Cb (8) 300 ns tF SDA and SCL fall time 20 +.1Cb (8) 300 ns tSU: S1, S2,WP S1, S2, and WP setup time 0.4 ms tHD: S1, S2,WP S1, S2, and WP hold time 0.4 ms Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR X4C105

13 FN8124.0 March 18, 2005 S1, S2, and WP Pin Timing Write Cycle Timing NOVRAM AC CHARACTERISTICS NOVRAM AC Conditions of Test NOVRAM Equivalent A.C Load Circuits tHD: S1,S2,WP SCL SDA IN S1, S2, and WP tSU: S1,S2,WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 3.3V 30pF 1596Ω 3093Ω X4C105

Table 2. NOVRAM Read Cycle Limits

15 FN8124.0 March 18, 2005 NOVRAM WRITE CYCLE SPECIFICATIONS NOVRAM Write Cycle Limits VCC = 3.0V-3.6V, TA = -40°C to +85°C Note: (10) t LZ and tOLZ min.; t SOE and tHOE min; and t HZ and t OHZ are periodically sampled and not 100% tested. t HZ max. and t OHZ max. are measured, with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. Symbol Parameter Min. Max. Unit tWC Write cycle time 120 ns tWC1 Write cycle time 170 ns tOES Output enable HIGH setup time 50 ns tOEH Output enable HIGH hold time 50 ns tCW Chip enable to end of write input 50 ns tCE Write setup time 0 ns tCH Write hold time 0 ns tWP Write pulse width 50 ns tWP1 Write pulse width 100 ns tWPH Write pulse HIGH recovery time 50 ns tDS Data setup to end of write 40 ns tDH Data hold time 0 ns tNDO New data output 50 ns tSOE(10) OE setup prior to operation in 2-wire mode 100 ms tHOE(10) OE hold following operation in 2-wire mode 100 ms tWZ Write enable to output in HIGH-Z 50 ns tOW Output active from end of write 0 ns tCHZ(10) Chip disable to output in high Z 0 50 ns tOHZ(10) Output disable to output in high Z 0 50 ns X4C105

16 FN8124.0 March 18, 2005 NOVRAM WE Controlled Write Cycle NOVRAM CE Controlled Write Cycle tCW tOEH tDH tCE tWP tDS OE WE D0-D3 CE tOES tCH tWC tWPH (Data I/O) O0-O3 (Data Out) Previous Valid Data tNDO New Valid Data Data Valid tCW tDH tWP tDS OE WE CE Data Valid tOEHtOES tCE tCH tWPH tWC O0-O3 (Data Out) Previous Valid Data tNDO New Valid Data D0-D3 (Data In) X4C105

17 FN8124.0 March 18, 2005 LOW VOLTAGE DETECT/POWER CYCLE PARAMETERS Low Voltage Detect and Output Pin Recall Symbols Parameters Min. Typ. Max. Unit VTRIP Reset trip voltage-blank 2.80 2.875 2.95 V tRPD VCC detect to reset active 500 ns tPURST Power-up reset time out delay (tPURST Option 1)-default 100 200 400 ms tF VCC fall time from VCC = 3V to VCC = 2.5V 100 µs tR VCC rise time from VCC = 2.5V to VCC = 3V 100 µs tOVT Output pins valid after VCC exceeds VTRIP 200 ns VRVALID Reset valid VCC 1V VCC VTRIP RST tPURST tPURST tR tF tRPD VRVALID O0-O3 Data Valid VCC(min) tOVTtOVT Data Valid X4C105

18 FN8124.0 March 18, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X4C105

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8124.0 March 18, 2005

Ordering Information

Blank = 3.3V ±10%, VTRIP = 2.8–2.95V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package V20 = 20 Lead TSSOP Device X4C105 X X –X 20-Lead TSSOP YYWW XXX Blank = 3.3V ±10%, 0 to +70°C, VTRIP = 2.8-2.95V X4C105 X4C105