X45620

X45620 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

FN8250.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X45620 Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

FEATURES

• Dual voltage monitoring
• Active low reset outputs
• Two standard reset threshold voltages —Factory programmable threshold
• Lowline Output — zero delayed POR
• Reset signal valid to V CC = 1V
• System battery switch-over circuitry
• Selectable watchdog timer
• 256Kbits of EEPROM
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with programmable Block Lock ™ protection —In circuit programmable ROM mode
• Minimize EEPROM programming time —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 400kHz 2-wire Interface
• 2.7V to 5.5V power supply operation
• Available package — 20-lead TSSOP
• Dual supervisor
• Battery switch and output

DESCRIPTION

The Intersil X45620 combines power-on reset control, battery switch circuit, watchdog timer, supply voltage supervision, secondary voltage supervision, block lock protect and serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET active for a period of time. This allows the powe r supply and oscillator to stabilize before the processor can execute code. A system battery switch circuit compares VCC (V1MON) with V BATT input and connects V OUT to whichever is higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X45620 can drive 50mA from VCC and 250µA from VBATT. The device switches to V BATT when V CC drops below the low VCC voltage threshold and VBATT > VCC. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode, Test & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power-on, GenerationVCC Monitor Reset Low Voltage Status Register Protect Logic EEPROM Watchdog Transition Detector WP

512 X 512

(V1MON) Battery Array Device Select Logic BATT-ON WDO VOUT VOUT (32K X 8 Bit) Data Sheet July 29, 2005

2 FN8250.0 July 29, 2005 DESCRIPTION (Continued) The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low volt age conditions, resetting the system when V CC (V1MON) falls below the mini- mum VCC trip point (V TRIP1). RESET is asserted until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply or monitors a second power supply voltage to provide a power fail warning. Intersil’s unique circuits allow the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher preci- sion. (Contact factory for custom V TRIP options) PIN CONFIGURATION

Ordering Information

VCC (V1MON) BATT-ON VOUT5 NC LOWLINE V2FAIL V2MON RESET/MR WDO VSS VBATT NC NC SCL SDA WP VCC Range V TRIP1 Range V TRIP2 Range Package Operating Temperature Range Part Number -40°C–85°C X45620V20I -40°C–85°C X45620V20I-2.7 PIN DESCRIPTION Pin Name Function 1 S0 Device Select Input. This pin has an internal pull down resistor. (>10MΩ typical) 2 S1 Device Select Input. This pin has an internal pull down resistor. (>10MΩ typical)

3 NC No internal connections

4L O W L I N E Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1 and immediately goes HIGH when VCC > VTRIP1.

5 NC No internal connections

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 7V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. X45620

3 FN8250.0 July 29, 2005

8 RESET

/MR Reset Output/Manual Reset Input. This is an Input/Output pin. RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. When RESET is active communication to the device is interrupt- ed. RESET remains active until VCC rises above the minimum VCC sense level for tPURST. RESET also goes active on power-up and remains active for tPURST after the power supply stabilizes. MR Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert- ed. When MR is released, the RESET remains asserted for tPURST, and then released. 9W D O Watchdog Output. WDO is an active low, open drain output which goes active whenever the watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.

10 V SS Ground

11 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output, requires the use of a pull-up resistor. 14 SCL Serial Clock. The SCL input is used to clock all data into and out of the device. 12–13 NC No internal connections 15 V BATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri- mary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect VBATT to ground. 16 V OUT Output Voltage. VOUT = VCC if VCC > VTRIP1. IF VCC < VTRIP1, then, VOUT = VCC if VCC > VBATT+0.03 VOUT = VBATT if VCC < VBATT-0.03 Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability. 17 BATT-ON Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when VOUT switches to VCC. It is used to drive a external P-channel FET when VCC = VOUT and current requirements are greater than 50mA. The purpose of this output is to drive an external FET to get higher operating currents when the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply enough voltage and current to keep SRAM devices from losing their data-there is no communication at this time.

18 NC No Connect

19 WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down resistor. (>10MΩ typical)

20 V CC

(V1MON) Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1 voltage, RESET and LOWLINE go ACTIVE. PIN DESCRIPTION (Continued) Pin Name Function X45620

4 FN8250.0 July 29, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with D.C. output current COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min Max Commercial 0°C 70°C Industrial -40°C +85°C Device Option Supply Voltage -2.7 2.7V-5.5V Blank 4.75V-5.5V D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsMin Typ (6) Max ICC1 VCC Supply Current (Active) (Excludes IOUT) Read Memory array (Excludes IOUT) Write nonvolatile Memory 1.5 3.0 mA SCL = 400kHz VOUT, RESET, LOWLINE = Open Note 1 ICC2 VCC Supply Current (Passive) (Excludes IOUT) 50 µA SDA = V CC, Any Input = VSS or VCC: VOUT, RESET, LOWLINE = Open, Note 2 ICC3 VCC Current (Battery Backup Mode) (Excludes IOUT) 1µ A V BATT = 2.8V, VOUT, RE- SET = Open, Note 4, 1 IBATT1 VBATT Current (Excludes IOUT)1 µ A V OUT = VCC, Note 4 IBATT2 VBATT Current (Excludes IOUT) (Battery Backup Mode) 50 µA V OUT = VBATT, VBATT =2 . 8 V VOUT, RESET = Open, Note 4 VOUT1 Output Voltage (VCC > VBATT + 0.03V or VCC > VTRIP1 VCC – 0.05 VCC – 0.5 VCC – 0.02 VCC – 0.2 V V IOUT = -5mA IOUT = -50mA VOUT2 Output Voltage (VCC < VBATT + 0.03V and VCC < VTRIP1) {Battery Backup} VBATT – 0.2 V I OUT = -250µA VOLB Output (BATT-ON) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) VBSH Battery Switch Hysteresis (VCC < VTRIP1) -30 mV mV Power-up Power-down, Note 4 VTRIP1 VCC Reset Trip Point Voltage 4.5 2.55 4.62 2.62 4.75 2.7 V X45620 X45620-2.7 VTRIP2 V2MON Reset Trip Point Voltage 2.55 1.7 2.62 1.75 2.7 1.8 V X45620 X45620-2.7 X45620

5 FN8250.0 July 29, 2005 Notes: (1) The device enters the Active state after any start, and rema ins active until 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL min. and VIH max. are for reference only and are not tested. (4) This parameter is guaranteed by characterization. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS VOLR Output (RESET, LOWLINE, WDO, V2FAIL) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V) Two Wire Interface VIL Input (SDA, S0, S1, SCL, WP) LOW Voltage -0.5 V CC x 0.3 V Note 3 VIH Input (SDA, S0, S1, SCL, WP) HIGH Voltage VCC x 0.7 V CC + 0.5 V Note 3 ILI Input Leakage Current (SDA, S1, S0, SCL, WP) ±10 µA VOLS Output (SDA) LOW Voltage 0.4 V I OL = 3.0mA (5V) IOL = 1.0mA (3V), Note 4 D.C. OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsMin Typ (6) Max Symbol Test Max Unit Conditions COUT Output Capacitance (SDA, RESET, V2FAIL, LOWLINE, BATT-ON, WDO)8 p F V OUT = 0V, Note 1, 4 CIN Input Capacitance (SDA, SCL, S0, S1, WP) 6 pF V IN = 0V, Note 1, 4 VCC SDA 30pF 1.53kΩ VCC 1.53kΩ 30pF BATT-ON RESET 4481ΩV2FAIL LOWLINE WDO Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X45620

6 FN8250.0 July 29, 2005 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Read & Write Cycle Limits Serial Output Timing POWER-UP TIMING (5) Notes: (5) t PUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are not 100% tested. (6) Typical values are for TA = 25°C and nominal supply voltage (5V) (7) Cb = total capacitance of one bus line in pF. Bus Timing Symbol Parameter Min Max Unit Test Conditions fSCL SCL clock frequency 400 kHz tIN Pulse width suppression time at inputs 50 ns Note 4 tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs Note 4 tBUF Time the bus must be free before a new transmission can start 1.3 µs Note 4 tLOW Clock LOW period 1.3 µs Note 4 tHIGH Clock HIGH period 0.6 µs Note 4 tSU:STA Start condition setup time 0.6 µs tHD:STA Start condition hold time 0.6 µs tSU:DAT Data in setup time 100 ns Note 4 tHD:DAT Data in hold time 0 µs Note 4 tSU:STO Stop condition setup time 0.6 µs Note 4 tDH Data output hold time 50 ns Note 4 Symbol Parameter Min Max Unit Test Conditions tR SDA and SCL rise time 20 + .1Cb 300 ns Note 4 tF SDA and SCL fall time 20 + .1Cb 300 ns Note 4 tSU:S0, S1, WP S0, S1, and WP Setup Time 0.6 ns Note 4 tHD:S0, S1, WP S0, S1, and WP Hold Time 0 ns Note 4 Cb Capacitive load for each bus line 400 pF Note 4, 7 Symbol Parameter Max Unit Test Conditions tPUR Power-up to Read Operation 1 ms Note 4 tPUW Power-up to Write Operation 5 ms Note 4 tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH X45620

7 FN8250.0 July 29, 2005 S0, S1, and WP Pin Timing Write Cycle Limits Notes: (8) t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X45620 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Write Cycle Timing tSU: S0, S1, WP SCL SDA IN S0, S1 and WP Slave Address Byte Clk 1 Clk 9 tHD: S0, S1, WP Symbol Parameter Min Typ (6) Max Unit Test Conditions TWC(8) Write Cycle Time — 5 10 ms Note 4 SCL SDA 8th Bit Word n ACK tWC Stop Condition Start Condition X45620

8 FN8250.0 July 29, 2005 Power-Up and Power-Down Timing VCC to LOWLINE Timings V2MON to V2FAIL Timings tVB1 RESET tVB2 tPURST tPURST tRPD VBATT VCC VBAT VOUT VTRIP1 VOUT VCC BATT-ON VCC LOWLINE VTRIP VBATT VTRIP1 VOH VOL VTRIP1 tR tRPD tRPD tF VTRIP2 tR tRPD2 tRPD2 tF V2MON V2FAIL X45620

9 FN8250.0 July 29, 2005 RESET Output Timing Notes: (9) This measurement is from 10% to 90% of the supply voltage. WDT Restart Timing Minimum WDT Restart Timing Symbol Parameter Min Typ (6) Max Unit Test Conditions tPURST RESET Time Out Period PUP = 0 PUP = 1 400 150 600 250 800 ms Note 4 t RPD VTRIP1 to RESET (Power-down only), VTRIP1 to LOWLINE 10 20 µs Note 4 tRPD2 VTRIP2 to V2FAIL 10 20 µs Note 4 tLR LOWLINE to RESET delay (Power-down only) 100 200 300 ns Note 4 tF VCC/V2MON Fall Time 1000 µs Note 4, 9 tR VCC/V2MON Rise Time 1000 µs Note 4, 9 VRVALID Reset Valid VCC 1V tVB1 VBATT + 0.03 V to BATT-ON (logical 0) 20 µs Note 4 tVB2 VBATT – 0.03 V to BATT-ON (logical 1) 20 µs Note 4 tHD:STA <tWDO tWDO tWDOtRST SCL SDA WDO tHD:STA WDT Restart tSU:STO WDT Restart tLOW tHIGH SCL SDA tHIGH X45620

processor to begin executing code. until V2MON returns and exceeds VTRIP2. Figure 1. Two Uses of Dual Voltage Monitoring

draw much less current than in their active mode. oscillations between supplies. cuits during normal operation. Figure 2. Example System Connection VCC > VTRIP1 Normal Operation. tion to the device is allowed.

12 FN8250.0 July 29, 2005 TWO WIRE SERIAL MEMORY The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features two wire and software protocol allowing operation on a simple four-wire bus. Two device select inputs (S 0–S1) allow up to four devices to share a common two wire bus. A Control Register at the highest address location, FFFFh, provides three write protection features: Soft- ware Write Protect, Block Lock Protect, and Program- mable ROM. The Software Write Protect feature prevents any nonvolatile writ es to the device until the WEL bit in the Control Register is set. The Block Lock Protection feature gives the user eight array block pro- tect options, set by programming three bits in the Con- trol Register. The Programmable ROM feature allows the user to install the device with WP tied to V CC, write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Program- mable ROM Mode by programming the WPEN bit HIGH in the Control Register. After this, the Block Locked por- tions of the array, including the Control Register itself, are protected from being erased if WP is high. Intersil EEPROMs are designed and tested for appli- cations requiring extended endurance. Inherent data retention is greater than 100 years. DETAILED PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typica l values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S 0, S1) The device select inputs (S0, S1) are used to set bits in the slave address. This allo ws up to four devices to share a common bus. These inputs can be static or actively driven. If used static ally they must be tied to V SS or V CC as appropriate. If actively driven, they must be driven with CMOS levels (driven to V CC or VSS) and they must be constant between each start and stop issued on the SDA bus. These pins have an active pull down internally and will be sensed as low if the pin is left unconnected. Write Protect (WP) WP must be constant between each start and stop issued on the SDA bus and is always active (not gated). The WP pin has an active pull down to disable the write protection when the input is left floating. The Write Protect input controls the Hardware Write Pro- tect feature. When held LOW, Hardware Write Protec- tion is disabled. When this input is held HIGH, and the WPEN bit in the Control Register is set HIGH, the Control Register is protected, preventing changes to the Block Lock Protection and WPEN bits. DEVICE OPERATION The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. Therefore, the devic e will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state cha nges during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 7 and 8. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. X45620

the device returns to the standby mode. first read or write operation must supply an address. Address Bytes as shown in Figure 10. Address Byte 0. See Figure 10. Figure 10. Device Addressing The device is capable of a 64 byte page write operation. mented by one. The page add ress remains constant.

1 S1 S0 R/W

immediately after the stop condition. the array. The partitions are described in Table 2. processor activity by monitoring the SCL and SDA pins. Status Register determines the watchdog timer period. writing to the status register. Note 1. Watchdog timer is shipped disabled. PURST time is set to 150ms at the factory. cycling the power to the device. is returned (ACK polling) complete the read operation. Table 2. Block Protect Bits

Table 3. Write Protect Enable Bit and WP Pin Function volatile cycle. The zeros in the data byte are required. changes to the control register). effect immediately following the last data bit. – The device is in the low power standby state. – The Write Enable Latch (WEL) is reset. Signal is active for tPURST. to the nonvolatile bits of the Control Register. 8 data bits and completion of the data ACK bit.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8250.0 July 29, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .252 (6.4) .300 (7.62) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X45620