X4323_06 INTERSIL | Alldatasheet

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Technical content

FN8122.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X4323, X4325 32k, 4k x 8 Bit CPU Supervisor with 32k EEPROM

FEATURES

  • Selectable watchdog timer
  • L o w VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
  • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog off —3mA active current
  • 32Kbits of EEPROM —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
  • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block Lock (1, 2, 4, 8 pages, all, none)
  • 400kHz 2-wire interface
  • 2.7V to 5.5V power supply operation
  • Available packages —8 Ld SOIC —8 Ld TSSOP
  • Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X4323, X4325 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Volt- age Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, t he interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Four industry standard V TRIP thresholds are available, however, Inter- sil’s unique circuits allow the threshold to be repro- grammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP RESET (X4323) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic Block Lock Control RESET (X4325) 4kb Data Sheet May 25, 2006

2 FN8122.1 May 25, 2006 PIN CONFIGURATION PIN FUNCTION VSS VCC SDA SCL3 8-Pin JEDEC SOIC WP RST/RST VCC SCL RST/RST VSS3 8WP SDA 8-Pin TSSOP Pin (SOIC) Pin (TSSOP) Name Function

13 S 0 Device Select Input

24 S 1 Device Select Input

35 R E S E T /

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain ac- tive until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET /RESET goes active on power-up- power-up and remains active for 250ms after the power supply stabilizes.

46 V SS Ground

57 S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the de- vice. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is al- ways active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET /RESET going active. 68 S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 71 W P Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register.

82 V CC Supply Voltage

X4323, X4325

3 FN8122.1 May 25, 2006

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP. RANGE (°C) PACKAGE PKG. DWG. # X4323S8Z-2.7 (Note) X4323 ZF X4325S8Z-2.7 (Note) X4325 ZF 0 to 70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323S8I-2.7 X4323 G X4325S8I-2.7 X4325 G -40 to 85 8 Ld SOIC (150 mil) MDP0027 X4323S8IZ-2.7 (Note) X4323 ZG X4325S8IZ-2.7 (Note) X4325 ZG -40 to 85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323V8-2.7 4323 F X4325V8-2.7 4325 F 0 to 70 8 Ld TSSOP (4.4mm) M8.173 X4323V8Z-2.7 (Note) 4323 FZ X4325V8Z-2.7 (Note) 4325 FZ 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323V8I-2.7 4323 G X4325V8I-2.7 4325 G -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X4323V8IZ-2.7 (Note) 4323 GZ X4325V8IZ-2.7 (Note) 4325 GZ -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323S8-2.7A X4323 AN X4325S8-2.7A X4325 AN 2.85 to 3.0 0 to 70 8 Ld SOIC (150 mil) MDP0027 X4323S8Z-2.7A (Note) X4323 ZAN X4325S8Z-2.7A (Note) X4325 ZAN 0 to 70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323S8I-2.7A X4323 AP X4325S8I-2.7A X4325 AP -40 to 85 8 Ld SOIC (150 mil) MDP0027 X4323S8IZ-2.7A (Note) X4323 ZAP X4325S8IZ-2.7A (Note) X4325 ZAP -40 to 85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323V8-2.7A 4323 AN X4325V8-2.7A 4325 AN 0 to 70 8 Ld TSSOP (4.4mm) M8.173 X4323V8Z-2.7A (Note) 4323 ANZ X4325V8Z-2.7A (Note) 4325 ANZ 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323V8I-2.7A 4323 AP X4325V8I-2.7A 4325 AP -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X4323V8IZ-2.7A (Note) 4323 APZ X4325V8IZ-2.7A (Note) 4325 APZ -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323S8 X4323 X4325S8 X4325 4.5 to 5.5 4.25 to 4.5 0 to 70 8 Ld SOIC (150 mil) MDP0027 X4323S8Z (Note) X4323 Z X4325S8Z (Note) X4325 Z 0 to 70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323S8I X4323 I X4325S8I X4325 I -40 to 85 8 Ld SOIC (150 mil) MDP0027 X4323S8IZ (Note) X4323 ZI X4325S8IZ (Note) X4325 ZI -40 to 85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323V8 4323 X4325V8 4325 0 to 70 8 Ld TSSOP (4.4mm) M8.173 X4323V8Z (Note)

4323 Z X4325V8Z

(Note) 4325 Z 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323V8I 4323 I X4325V8I 4325 I -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X4323V8IZ (Note)

4323 IZ X4325V8IZ

(Note) 4325 IZ -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323S8-4.5A X4323 AL X4325S8-4.5A X4325 AL 4.5 to 4.75 0 to 70 8 Ld SOIC (150 mil) MDP0027 X4323S8Z-4.5A (Note) X4323 ZAL X4325S8Z-4.5A (Note) X4325 ZAL 0 to 70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323S8I-4.5A X4323 AM X4325S8I-4.5A X4325 AM -40 to 85 8 Ld SOIC (150 mil) MDP0027 X4323S8IZ-4.5A (Note) X4323 ZAM X4325S8IZ-4.5A (Note) X4325 ZAM -40 to 85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4323, X4325

4 FN8122.1 May 25, 2006 X4323V8Z-4.5A (Note) 4323 ALZ X4325V8Z-4.5A (Note) 4325 ALZ 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X4323V8I-4.5A 4323 AM X4325V8I-4.5A 4325 AM -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X4323V8IZ-4.5A (Note) 4323 AMZ X4325V8IZ-4.5A (Note) 4325 AMZ -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP. RANGE (°C) PACKAGE PKG. DWG. # X4323, X4325

pin active. This signal provides several benefits. to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power-up. /RESET allowing the system to begin operation. from operating in a power fail or brownout condition. CC returns and exceeds VTRIP for 200ms. allowed and no nonvolatile write operation can start. goes active are allowed to finish. memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. Figure 1. Set V

Figure 4. VTRIP Programming Sequence data byte is allowed for each register write operation. the Control Register" on page 9.

time by performing a random read at address FFFFh. Only one byte is read by each register read operation. required to end this operation. tile latch that powers up in the LOW (disabled) state. tion immediately after the stop condition. Watchdog Timer. The options are shown below. written and the block protect bits cannot be changed. long as the WP pin is held HIGH. Table 1. Write Protect Enable Bit and WP Pin Function

Figure 10. Writing 12-bytes to a 64-byte Page Starting at Location 60. contents of the array will not be effected. can then proceed with the read or write operation. Refer to the flow chart in Figure 11. Figure 11. Acknowledge Polling Sequence

4 Bytes

8 Bytes

needs to read, but is not ready for the data. acknowledge and then issuing a stop condition. address n followed by the data from address n + 1. Figure 14. Sequential Read Sequence – next two bits are the device address. write operation. Refer to Figure 15. is undefined on a power-up condition.

Figure 15. X4323, X4325 Addressing – The device is in the low power standby state. – SDA pin is the input mode. – RESET Signal is active for tPURST. – The WEL bit must be set to allow write operations. HIGH will prevent all writes to the Control Register. array from write operations.

16 FN8122.1 May 25, 2006 ABSOLUTE MAXIMUM RATINGS COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns afte r any stop, except those that initiate a nonvolatile write cycle; t WC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. Symbol Parameter VCC = 2.7 to 5.5V Unit Test ConditionsMin. Max. ICC1(1) Active Supply Current Read 1.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHz, SDA = CommandsICC2(1) Active Supply Current Write 3.0 mA ISB(2) Standby Current DC (WDT off) 1 µA V SDA = VSCL = VSB Others = GND or VSB ISB(2) Standby Current DC (WDT on) 20 µA V SDA = VSCL = VSB Others = GND or VSB ILI Input Leakage Current 10 µA V IN = GND to VCC ILO Output Leakage Current 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage -0.5 V CC x 0.3 V VIH(3) Input nonvolatile V CC x 0.7 V CC + 0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage 0.4 V I OL = 3.0mA (2.7-5.5V) RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Option Supply Voltage Limits -2.7 and -2.7A 2.7V to 5.5V Blank and -4.5A 4.5V to 5.5V X4323, X4325

17 FN8122.1 May 25, 2006 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (1) Typical values are for T A = 25°C and VCC = 5.0V (2) Cb = total capacitance of one bus line in pF. Symbol Parameter Max. Units Test Conditions COUT (4) Output Capacitance (SDA, RST/RST)8 p F V OUT = 0V CIN (4) Input Capacitance (SCL, WP) 6 pF V IN = 0V 1533Ω 100pF For VOL= 0.4V and IOL = 3 mASDA or RESET Input pulse levels 0.1V CC to 0.9VCC Input rise and fall times 10ns Input and output timing levels 0.5V CC Output load Standard output load Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb 300 ns tF SDA and SCL Fall Time 20 +.1Cb 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF X4323, X4325

18 FN8122.1 May 25, 2006 TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Notes: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min. Typ. (1) Max. Unit tWC(1) Write Cycle Time 5 10 ms X4323, X4325

19 FN8122.1 May 25, 2006 Power-Up and Power-Down Timing RESET Output Timing Notes: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset Trip Point Voltage, X4323-4.5A, X4325-4.5A Reset Trip Point Voltage, X4323, X4325 Reset Trip Point Voltage, X4323-2.7A, X4325-2.7A Reset Trip Point Voltage, X4323-2.7, X4325-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V t PURST Power-up Reset Time OUT 100 250 400 ms tRPD(8) VCC Detect to Reset/Output 500 ns tF(8) VCC Fall Time 100 µs tR(8) VCC Rise Time 100 µs VRVALID Reset Valid VCC 1V VCC tPURST tR tF tRPD

0 Volts

(X4323) (X4325) tPURST VRVALID tRSP<tWDO tRST RESET SDA tRSP Note: All inputs are ignored during the active reset period (tRST). tRST SCL tRSP>tWDO tRSP>tWDO X4323, X4325

20 FN8122.1 May 25, 2006 RESET Output Timing VTRIP Programming Timing Diagram (WEL = 1) VTRIP Programming Parameters Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 250 650 1.5 400 850 ms ms sec t RST Reset Time Out 100 250 400 ms Parameter Description Min. Max. Unit tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 2.55 4.75 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25°C.] -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. VCC (VTRIP) WP tTSU tTHD tVPHtVPS VP VTRIP tVPO SCL SDA A0h 01h or 03h tRP 00h 00h X4323, X4325

21 FN8122.1 May 25, 2006 X4323, X4325 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8122.1 May 25, 2006 X4323, X4325 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7 α 0o 8o 0o 8o - Rev. 1 12/00