X40626V14I

X40626 XICOR | Alldatasheet

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REV 1.1.15 2/11/04 Characteristics subject to change without notice. 1 of 23 www.xicor.com 64K X40626 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM

FEATURES

• Dual voltage monitoring 2Mon operates independent of V CC
• W atchdog timer with selectable timeout intervals
• L o w V CC detection and reset assertion — Four standard reset threshold voltages — User programmable V TRIP threshold — Reset signal valid to V CC =1V
• L ow power CMOS — 20µA max standby current, watchdog on — 1µA standby current, watchdog OFF
• 64Kbits of EEPROM — 64 byte page size
• Built-in inadvertent write protection —P ower-up/power-down protection circuitry —P rotect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block Lock protection
• 400kHz 2-wire interface — Slave addressing supports up to 4 devices on the same bus
• 2.7V to 5.5V power supply operation
• A vailable Packages — 14-lead SOIC — 14-lead TSSOP

DESCRIPTION

The X40626 combines four popular functions, Power-on Reset Control, Watchdog Timer, Dual Supply Voltage Supervision, and Serial EEPROM Memory in one pack- age. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabi- lize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontrol- ler fails to restart a timer within a selectable time-out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the set minimum V CC trip point. RESET is asserted until V CC returns to proper BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power on and Generation VTRIP RESET Reset Low Voltage Status Register Protect Logic 64KB Watchdog Transition Detector WP VCC Threshold Reset logic Block Lock Control V2 Monitor Logic VTRIP2 V2MON V2FAIL EEPROM Array Preliminary Information

REV 1.1.15 2/11/04 Characteristics subject to change without notice. 2 of 23 www.xicor.com operating level and stabilizes. Four industry standard Vtrip thresholds are available. However, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock Protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software protocol allowing operation on an I C bus. The device utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 100,000 page write cycles and a minimum data retention of 100 years. PIN CONFIGURATION VSS VCC V2MON WP3

14 Pin SOIC/TSSOP

1, 4, 6, 13 NC No Internal Connections Device Select Input Device Select Input

5 RESET

RESET is an active LOW, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the min- imum V CC sense level for typically 200ms. RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time- out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes active on power up and remains active for typically 200ms after the power supply stabilizes. SS Ground

8 SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out period results in RESET going active.

9 SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

10 V2FAIL

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V TRIP2 and goes HIGH when V2MON exceeds V TRIP2 . There is no power up reset delay circuitry on this pin. This circuit works independently from the Low V CC reset and battery switch circuits. Connect V2FAIL to VSS when not used.

11 V2MON

V2 Voltage Monitor Input. When the V2MON input is less than the V TRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V SS or V CC when not used. There is no hysteresis in the V2MON comparator circuits. 12 WP Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. 14 V CC Supply Voltage

Characteristics subject to change without notice. signal provides several benefits. to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power up. RESET allowing the system to begin operation. bits, or they may be “locked” by tying the WP pin HIGH. memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. point before setting the new value. Figure 1. Set V

Figure 4. VTRIP Programming Sequence

The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer set- tings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed at address FFFFh. It can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register" below. The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X40626 will not acknowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X40626 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits - (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block pro- tect bits will prevent write operations to one of eight segments of the array. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Write Protect Enable These devices have an advanced Block Lock scheme that protects one of eight blocks of the array when enabled. It provides hardware write protection through the use of a WP pin and a nonvolatile Write Protect Enable (WPEN) bit. Four of the 8 protected blocks match the original Block Lock segments and this pro- tection scheme is fully compatible with the current devices using 2 bits of block lock control (assuming the BP2 bit is set to 0). The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the programmable Hardware Write Protect feature. Hard- ware Write Protection is enabled when the WP pin and the WPEN bit are HIGH and disabled when either the WP pin or the WPEN bit is LOW. When the chip is Hard- ware Write Protected, nonvolatile writes as well as to the block protected sections in the memory array cannot be written. Only the sections of the memory array that are 76 5 4 3 2 1 0 WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2 BP2 BP1 BP0 Protected Addresses (Size) Array Lock

000 None (factory setting) None

001 1800h - 1FFFH (2K bytes) Upper 1/4 (Q4) 010 1000h - 1FFFH (4K bytes) Upper 1/2 (Q3,Q4) 011 0000h - 1FFFH (8K bytes) Full Array (All) 100 0 0 0 h - 03FH (64 bytes) First Page (P1) 101 0 0 0 h - 07FH (128 bytes) First 2 pgs (P2) 110 0 0 0 h - 0FFH (256 bytes) First 4 pgs (P4) 111 0 0 0 h - 1FFH (512 bytes) First 8 Pgs (P8) WD1 WD0 Typ. Watchdog Time-out Period 00 1.4 Seconds 01 600 milliseconds 10 200 milliseconds

11 Disabled (factory setting)

Table 1. Write Protect Enable Bit and WP Pin Function ceeded by a start and ended with a stop). atile write cycle it will take up to 10ms to complete. so aborts the write operation and returns a NACK. operate as slaves in all applications.

Figure 9. Page Write Operation Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around).

0 S1S0

4 Bytes

8 Bytes

Figure 14. Sequential Read Sequence operation. Refer to Figure 15. the device outputs an acknowledge on the SDA line. is 00H on a power up condition.

Figure 15. X40626 Addressing – The device is in the low power standby state. –S DA pin is in the input mode. Signal is active for tPURST. – The WEL bit must be set to allow write operations. HIGH will prevent all writes to the Control Register. array from write operations.

Table 2. Recommended Operating Conditions Ratings” may cause permanent damage to the device. ditions for extended periods may affect device reliability. Slave Address Byte are incorrect; or (b) 200nS after a stop ending a read operation. (2) The device enters the Active state after any start, and remains active until tWC after a stop ending a write operation.

CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Notes: (4) This parameter is periodically sampled and not 100% tested. Symbol Parameter Max. Units Test Conditions COUT (4) Output Capacitance (SDA, RESET, V2FAIL)8 p F VOUT = 0V CIN (4) Input Capacitance (SCL, WP, S0, S1) 6 pF V IN = 0V EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS V2MON 1.53KΩ V2FAIL 30pF SDA RESET 1533Ω 30pF Input pulse levels 0.1V CC to 0.9VCC Input rise and fall times 10ns Input and output timing levels 0.5V CC Output load Standard Output Load A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V (2) Cb = total capacitance of one bus line in pF . Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 400 KHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 + 0.1Cb (2) 300 ns tF SDA and SCL Fall Time 20 + 0.1Cb (2) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF

Nonvolatile Write Cycle Timing Notes: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (1) Max. Units tWC (1) Write Cycle Time 5 10 mS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th bit of Last Byte ACK Stop Condition Start Condition

Power-Up and Power-Down Timing RESET Output Timing Notes: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET Timing Symbol Parameter Min. Typ. Max. Units tPURST Power-up Reset Timeout 100 200 400 ms tRPD (8) VCC Detect to Reset/Output (Falling Edge) 500 ns tF (8) VCC/V2MON Fall Time 100 µs tR (8) VCC/V2MON Rise Time 100 µs VRVALID (8) Reset Valid VCC or V2FAIL Valid V2MON 1.0 V VTRIP Range Voltage Range over which V TRIP/VTRIP2 can be set 2.0 V CC V VCC/V2MON tPURST tR tF tRPD

0 Volts

< tWDO tRST RESET SDA Start tWDO tRST SCL Timer Start tRSP Timer Restart Timer Start Start

VTRIP Programming Timing Diagram (WEL = 1) Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period, WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 Disabled 100 450 1.0 Disabled 200 600 1.4 Disabled 400 850 2.0 Factory Setting ms ms sec t RST Reset Timeout 100 250 400 ms SCL SDA 0001H*: set VTRIP 00h VCC/V2MON (VTRIP/VTRIP2) WP tTSU tTHD tVPS VP tVPO AS1S000h 01 2 7 0 7 0 7 0 7 tWC Start 000DH: set VTRIP2 0003H: Resets VTRIP 000FH: Resets VTRIP2 data VCC/V2MON

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.020 (0.51) Pin 1 Pin 1 Index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-Lead Plastic Small Outline Gullwing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 0.250" 0.050" Typical 0.030" Typical

14 PlacesFOOTPRINT

0.050" Typical

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Ordering Information

(Active LOW) Park Mark -40°C–85°C X40626S14I–4.5A AM 14L TSSOP 0°C–70°C X40626V14–4.5A AL -40°C–85°C X40626V14I–4.5A AM -40°C–85°C X40626S14I I 14L TSSOP 0°C–70°C X40626V14 blank -40°C–85°C X40626V14I I -40°C–85°C X40626S14I–2.7A AP 14LTSSOP 0°C–70°C X40626V14–2.7A BN -40°C–85°C X40626V14I–2.7A AP -40°C–85°C X40626S14I–2.7 G 14L TSSOP 0°C–70°C X40626V14–2.7 F -40°C–85°C X40626V14I–2.7 G 14-Lead SOIC/TSSOP X40626 X YYWWXX S = SOIC WW – Workweek YY – Year V = TSSOP XX – Part Mark

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2004 Patents Pending